YGV639 Datasheet, PDF (29/34 Pages) YAMAHA CORPORATION – Video Controller 1 with Enhanced Functions

YGV639
Pattern Memory Interface
No.
Items
Symbol Min
Typ.
Max Unit Note
1 MA25-0: output delay time from SYCLK
t_dMA
2 ^{MOE_N: output delay time from SYCLK}
t_dOE
2
3 MWE_N: output delay time from SYCLK
t_dWE
2
4 MD15-0 : input setup time to SYCLK
t_sMD
4
5 MD15-0 : input hold time from SYCLK
t_hMD
0
6 MD15-0 : output delay time from SYCLK
t_dMD
7 MA25-0: hold time from MOE_N
t_hMAR
0
8 MD15-0 : input hold time from MOE_N, MA25-0
t_hMDI
0
9 MA25-0: hold time from MWE_N
t_hMAW
0
10 MD15-0 : hold time from MWE_N
t_hMDO
1
11 MD15-0 : turn off time from MWE_N
t_offMDO
1
12 Output turn off/on time from RAHZ_N
t_on/offRA
Note 1) SYCLK is an internal clock.
14
1
14
1
14
1
1
1
24
ns ¹
10
25
Memory access cycle
i) Random read cycle
SYCLK
1
1
MA25-0
MOE_N
MWE_N
MD15-0
2
2
7
3
8
4
5
Note: After a read access, values of MA25-0, MOE_N are held until the pattern memory is accessed again.
ii) Write Cycle
SYCLK
1
1
MA25-0
2
MOE_N
9
3
3
MWE_N
11
6
10
MD15-0
Note: After a write access, the value of MA25-0 is held until the pattern memory is accessed again.
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