YGV639 Datasheet, PDF (12/34 Pages) YAMAHA CORPORATION – Video Controller 1 with Enhanced Functions

YGV639
(4) Connect a decoupling capacitor between VDD33(pin48) and VSS(pin51).
(5) Board’s GND pattern must be wide enough to prevent the interference from other signals. Connect this
GND to VSS(pin51).
VC1E’s electrical characteristics were determined based on the assumption that a X'tal resonator is to be
connected to XIN/XOUT or X'tal oscillator is to XIN. Therefore, it is recommended to use a crystal resonator
or crystal oscillator. Use a X'tal resonator or X'tal oscillator with the allowable frequency deviation
(including temperature characteristics) of ±100ppm.
„ Ceramic Resonator
If using a ceramic resonator, the following points should be considered.
● Use a ceramic resonator with the same jitter performance as that of a crystal resonator.
● Ceramic resonators have relatively bigger allowable frequency deviation and frequency
temperature characteristics than those of a crystal resonator.
Such variation is not considered in the design; therefore, the system clock frequency should be within the
range of the specification (83.16MHz or less for VC1E) even if the frequency varies.
Dot Clock Input Pin
DTCKIN (Input)
When a dot clock is present in the system, this dot clock can be directly input to DTCKIN pin as a dot
clock.
The pin input is enabled when DTCKS_N=“L.” When DTCKS_N=“H,” a dot clock is generated by the
clock input to XIN pin. At this time, connect VDD33 or GND to DTCKIN pin. A clock frequency up to
40MHz can be input into DTCKIN pin.
Dot Clock Input Select Pin
DTCKS_N (Input)
This is the pin to select which one of either XIN or DTCKIN pin should be used for supplying the internal
dot clock. This pin is low active. Be sure to determine the level of the input signal to this pin during the reset
(RESET_N pin=“L”) at power-on, and do not change the state while the power has been already established.
PLL Control Pin
PLLCTL3-0 (Input)
These pins set a multiplication ratio of the built-in PLL that generates a system clock. Be sure to determine
the level of the input signals to the pins during the reset (RESET_N pin=“L”) at power-on, and do not change
the state while the power has been already established. PLLCTL3-1 are dual-purpose pins for LOADH,
STARTH, and OUTENV, respectively. When using a built-in timing controller, it functions as LOADH,
SHARTH, and OUTENV.
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