YGV639 Datasheet, PDF (14/34 Pages) YAMAHA CORPORATION – Video Controller 1 with Enhanced Functions

YGV639
Interrupt Pin
INT_N (Open Drain Output)
An interrupt request signal is output. INT_N signal is asserted when a flag enabled by the internal register
is set to “1.” When the flag is reset by the writing to the flag bit or when the interrupt enable bit is set to “0,”
INT_N signal is negated and becomes high impedance state. This pin is low active. Since this pin is an
open-drain output, a wired-OR connection with similar interrupt signals can be made. Pull up INT_N pin
outside the device as no pull-up resistor is provided.
CPU Interface Select Pin
SER_N (Input)
CPU interface selection pin. When choosing the serial interface, set to “L.” When choosing the parallel
interface, set to “H.” This pin is low active.
An input signal level should be settled during the period of RESET_N pin=“L” at power-on and must not
be changed while the power is ON.
Serial Interface Chip Select Input Pin
SCS_N (Input)
This is used as the chip select input pin when serial interface is selected. SDIN and SCLK pins become
enabled when this signal is in active state. This pin is low active.
This pin is a dual-purpose pin. When using the parallel Interface, it functions as CS_N pin.
Serial Data Input Pin
SDIN (Input)
This pin is used as the serial data input pin when serial interface is selected.
This pin is a dual-purpose pin. When using the parallel Interface, it functions as RD_N pin.
Serial Data Output Pin
SDOUT (3-State Output)
This pin is used as the serial data output pin when serial interface is selected.
This pin is a dual-purpose pin. When using the parallel interface, it functions as WAIT_N pin.
Serial Clock Input Pin
SCLK (Input)
This pin is used as the serial clock input pin when serial interface is selected.
This pin is a dual-purpose pin. When using the parallel interface, it functions as WR_N pin.
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