YGV639 Datasheet, PDF (28/34 Pages) YAMAHA CORPORATION – Video Controller 1 with Enhanced Functions

YGV639
Serial interface chip select
No.
Items
Symbol
Min.
Typ.
Max.
Unit Note
1 SCLK Clock Cycle Time
t_wSCLK
200
1
2 SCLK Clock High Level Pulse Width
t_whSCLK
100
1
3 SCLK Clock Low Level Pulse Width
t_wlSCLK
100
1
4 SCS_N: setup time
t_sSCS
25
5 SCS_N: hold time
t_hSCS
25
ns
6 SDIN: setup time
t_sSDI
25
7 SDIN: hold time
t_hSDI
25
8 SDOUT: output data delay time
t_dSDO
100
2
9 SDOUT: turn off time
t_offfSDO
20
10 SCS_N: pulse inhibit time
t_iSCS
400
Note 1) In the initialization, the 2-divided clock of XIN is used for the system clock. And, SCLK is sampled
twice by the system clock. Therefore, the minimum value of t_wSCLK becomes XIN cycle×8 (t_XIN × 8),
and minimum values of t_whSCLK and t_wlSCLK become XIN cycle × 4 (t_XIN × 4). Compare it with the
value defined in the above table and use the larger value.
Note 2) In the initialization, the maximum value of t_dSDO becomes XIN cycle × 6+100ns (t_XIN × 6 + 100ns).
SCS_N
4
SCLK
SDIN
SDOUT ^Hi-Z
1
3
2
6
7
8
8
5
9
10
SCS_N
SCLK
28