YGV639 Datasheet, PDF (16/34 Pages) YAMAHA CORPORATION – Video Controller 1 with Enhanced Functions

YGV639
Monitor Interface
These pins output picture data or timing signals to an external monitor.
Digital Picture Interface Pins
DR5-0, DG5-0, DB5-0 (Output)
These pins output digital R, G, and B signals of display data in synchronization with DOTCLK.
Vertical Synchronization Signal Output Pin
VSYNC_N (Output)
The vertical sync signal is output in synchronization with DOTCLK.
This pin’s activation state is selectable by the register setting.
● When the register (R#6:REVSY) is “0”: Low-active
● When the register (R#6:REVSY) is “1”: High-active
This pin is dual-purpose pin. When using the built-in timing controller, it functions as POL.
Horizontal / Composite Synchronization Signal Output Pin
HCSYNC_N (Output)
Horizontal or composite sync signal is output in synchronization with DOTCLK. Which signal should be
output is specified by the resistor (R#6: CSYOE).
This pin’s activation state is selectable by the register setting.
● When the register (R#6:REVSY) is “0”: Low-active
● When the register (R#6:REVSY) is “1”: High-active
This pin is dual-purpose pin. When using the built-in timing controller, it functions as CLKV.
Blank Signal Output Pin
BLANK_N (Output)
A signal that indicates a blank period is output in synchronization with DOTCLK. This signal can be used
when needing the signal (DE) which indicates a display period in an LCD panel etc.
This pin is dual-purpose pin. When using the built-in timing controller, it functions as STARTV.
Dot Clock Output Pin
DOTCLK (Output)
This pin outputs a dot clock. The dot clock used in VC1E is output. The following three ways are
selectable.
(1) Outputs an input clock to XIN pin as is or in frequency-divided form
(2) Outputs a PLL output clock as is or in frequency-divided form
(3) Outputs an input clock to DTCKIN pin as is
DOTCLK has the inversion output function. This is implemented by selecting the clock reversed by the
group selector just before outputting an internal dot clock to DOTCLK pin. Set DOTCLK inversion function
so that it meets each signal's Set-up/Hold time regulation of your monitor with respect to DOTCLK.
This pin output optimizes the drive capability to QVGA, dotclock frequency of approx. 6.36MHz. When
using a dot clock frequency of approx. 20MHz or more, it is recommended to add a clock buffer to the board.
And, when LCD’s input capacitance is large, the waveform may get distorted; therefore, check the waveform
by using an actual terminal.
Vertical Clock Output Pin
CLKV (Output)
When using the built-in timing controller, it outputs a vertical clock. This pin is dual-purpose pin. When
not using the built-in timing controller, it functions as HCSYNC_N.
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