XC3S2000-5FGG456C Datasheet, PDF (98/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Miscellaneous DCM Timing
Table 64: Miscellaneous DCM Timing
Symbol
Description
DCM_INPUT_CLOCK_STOP
DCM_RST_PW_MIN
Maximum duration that the CLKIN and
CLKFB signals can be stopped^(1,2)
Minimum duration of a RST pulse width
DCM_RST_PW_MAX⁽³⁾
Maximum duration of a RST pulse width^(1,2)
DCM_CONFIG_LAG_TIME⁽⁴⁾
Maximum duration from V_CCINT applied to
FPGA configuration successfully completed
(DONE pin goes High) and clocks applied to
DCM DLL^(1,2)
DLL
Frequency
Mode
Any
Temperature Range
Commercial Industrial
100
100
Any
3
3
Low
N/A
N/A
High
N/A
10
Low
N/A
N/A
High
N/A
10
Units
ms
CLKIN
cycles
seconds
seconds
minutes
minutes
Notes:
1. These limits only apply to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected. Required due to effects of device cooling: see “Momentarily Stopping CLKIN”
in Chapter 3 of UG331.
2. Industrial-temperature applications that use the DLL in High-Frequency mode must use a continuous or increasing operating frequency. The
DLL under these conditions does not support reducing the operating frequency once establishing an initial operating frequency.
3. This specification is equivalent to the Virtex-4 FPGA DCM_RESET specification.
4. This specification is equivalent to the Virtex-4 FPGA TCONFIG specification.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
98