XC3S2000-5FGG456C Datasheet, PDF (146/272 Pages) Xilinx, Inc – Introduction and Ordering Information

TQ144 Footprint
X-Ref Target - Figure 46
Spartan-3 FPGA Family: Pinout Descriptions
IO_L01P_7/VRN_7 1
IO_L01N_7/VRP_7 2
VCCO_LEFT 3
IO/VREF_7 4
IO_L20P_7 5
IO_L20N_7 6
IO_L21P_7 7
IO_L21N_7 8
GND 9
IO_L22P_7 10
IO_L22N_7 11
IO_L23P_7 12
IO_L23N_7 13
IO_L24P_7 14
IO_L24N_7 15
GND 16
IO_L40P_7 17
IO_L40N_7/VREF_7 18
VCCO_LEFT 19
IO_L40P_6/VREF_6 20
IO_L40N_6 21
GND 22
IO_L24P_6 23
IO_L24N_6/VREF_6 24
IO_L23P_6 25
IO_L23N_6 26
IO_L22P_6 27
IO_L22N_6 28
GND 29
IO_L21P_6 30
IO_L21N_6 31
IO_L20P_6 32
IO_L20N_6 33
VCCO_LEFT 34
IO_L01P_6/VRN_6 35
IO_L01N_6/VRP_6 36
X
Bank 0
VCCO for Top Edge
Bank 1
Bank 5
(no DCI)
VCCO for Bottom Edge
Bank 4
108 IO_L01N_2/VRP_2
107 IO_L01P_2/VRN_2
106 VCCO_RIGHT
105 IO_L20N_2
104 IO_L20P_2
103 IO_L21N_2
102 IO_L21P_2
101 GND
100 IO_L22N_2
99 IO_L22P_2
98 IO_L23N_2/VREF_2
97 IO_L23P_2
96 IO_L24N_2
95 IO_L24P_2
94 GND
93 IO_L40N_2
92 IO_L40P_2/VREF_2
91 VCCO_RIGHT
90 IO_L40N_3/VREF_3
89 IO_L40P_3
88 GND
87 IO_L24N_3
86 IO_L24P_3
85 IO_L23N_3
84 IO_L23P_3/VREF_3
83 IO_L22N_3
82 IO_L22P_3
81 GND
80 IO_L21N_3
79 IO_L21P_3
78 IO_L20N_3
77 IO_L20P_3
76 IO
75 VCCO_RIGHT
74 IO_L01N_3/VRP_3
73 IO_L01P_3/VRN_3
DS099-4_08_121103
Figure 46: TQ144 Package Footprint (Top View). Note pin 1 indicator in top-left corner and logo orientation.
51 I/O: Unrestricted, general-purpose user I/O
14
DCI: User I/O or reference resistor input for
bank
7 CONFIG: Dedicated configuration pins
12
DUAL: Configuration pin, then possible
user I/O
8
GCLK: User I/O or global clock buffer
input
12
VREF: User I/O or input voltage reference for
bank
12 VCCO: Output voltage supply for bank
4 JTAG: Dedicated JTAG port pins
4 VCCINT: Internal core voltage supply (+1.2V)
0 N.C.: No unconnected pins in this package 16 GND: Ground
4 VCCAUX: Auxiliary voltage supply (+2.5V)
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
146