XC3S2000-5FGG456C Datasheet, PDF (97/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Phase Shifter (PS)
Phase shifter operation is only supported if the DLL is in low-frequency mode, see Table 58. Fixed phase shift requires ISE
software version 10.1.03 (or later).
Table 62: Recommended Operating Conditions for the PS in Variable Phase Mode
Symbol
Description
Frequency Mode/
F_CLKIN Range
Speed Grade
-5
-4
Min
Max
Min
Max
Operating Frequency Ranges
PSCLK_FREQ Frequency for the
Low
(F_PSCLK)
PSCLK input
Input Pulse Requirements
1
167
1
167
PSCLK_PULSE PSCLK pulse width
Low
F_CLKIN ≤ 100 MHz
40%
as a percentage of
the PSCLK period
F_CLKIN > 100 MHz
45%
60%
55%
40%
45%
60%
55%
Units
MHz
-
-
Table 63: Switching Characteristics for the PS in Variable or Fixed Phase Shift Mode
Symbol
Description
Frequency Mode/
F_CLKIN Range
Speed Grade
-5
-4
Min Max Min Max
Units
Phase Shifting Range
FINE_SHIFT_RANGE Phase shift range
Low
–
10.0
–
10.0 ns
Lock Time
LOCK_DLL_PS
When using the PS in conjunction 18 MHz ≤ F_CLKIN ≤ 30 MHz
–
3.28
–
3.28 ms
with the DLL: The time from
deassertion at the DCM’s Reset
30 MHz < F_CLKIN ≤ 40 MHz
–
2.56
–
2.56 ms
input to the rising transition at its
LOCKED output. When the DCM
40 MHz < F_CLKIN ≤ 50 MHz
–
1.60
–
1.60 ms
is locked, the CLKIN and CLKFB ^{50 MHz < F}CLKIN ^{≤ 60 MHz}
–
1.00
–
1.00 ms
signals are in phase.
60 MHz < F_CLKIN ≤ 165 MHz –
0.88
–
0.88 ms
LOCK_DLL_PS_FX When using the PS in conjunction
Low
with the DLL and DFS: The time
from deassertion at the DCM’s
Reset input to the rising transition
at its LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase.
– 10.40 – 10.40 ms
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32 and Table 62.
2. The PS specifications in this table apply when the PS attribute CLKOUT_PHASE_SHIFT= VARIABLE or FIXED.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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