XC3S2000-5FGG456C Datasheet, PDF (140/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
CP132 Footprint
X-Ref Target - Figure 45
VCCO_TOP for Top Edge Outputs
Bank 0
Bank 1
1
2
3
4
5
6
7
8
9
10 11 12 13 14
A
TDI
PROG_B
I/O
L01N_0
VRP_0
VCCO_
TOP
VCCAUX
I/O
L30P_0
I/O
L32N_0
GCLK7
I/O
L32N_1
GCLK5
I/O
L32P_1
GCLK4
I/O
L31P_1
I/O
L28N_1
I/O
L27P_1
I/O
L01N_1
VRP_1
TMS
I/O
B L01P_7
VRN_7
I/O _{HSWAP_}
L01N_7
EN
VRP_7
GND
I/O
L27P_0
I/O
L30N_0
I/O
L31P_0
VREF_0
VCCO_
TOP
GND
VCCINT
I/O
L28P_1
VCCO_
TOP
I/O
L01P_1
VRN_1
TCK
C
I/O
L21N_7
GND
VCCO_
LEFT
I/O
L01P_0
VRN_0
I/O
VCCINT
L27N_0
I/O
L31N_0
I/O
L32P_0
GCLK6
I/O
L31N_1 VCCAUX
VREF_1
I/O
L27N_1
GND
TDO
I/O
L01P_2
VRN_2
D ^I/O
I/O
I/O
L22N_7 L22P_7 L21P_7
I/O
L01N_2
VRP_2
VCCO_
RIGHT
GND
E
I/O
L24P_7
I/O
L23N_7
I/O
L23P_7
I/O
I/O
I/O
L20N_2 L20P_2 L21N_2
F GND
I/O
I/O
L40P_7 L24N_7
I/O
G L40N_7
VREF_7
VCCO_
LEFT
I/O
L40P_6
VREF_6
H
I/O
L40N_6
I/O
L24P_6
I/O
L24N_6
VREF_6
I/O
L21P_2
I/O
L23N_2
VREF_2
I/O
L23P_2
I/O
I/O
I/O
L24N_2 L24P_2 L40N_2
I/O
L40P_2
VREF_2
VCCO_
RIGHT
I/O
L40N_3
VREF_3
J ^I/O
I/O
I/O
L23P_6 L23N_6 L22P_6
I/O
I/O
L24N_3 L40P_3
GND
K ^I/O
I/O
I/O
L22N_6 L20P_6 L20N_6
I/O
L23P_3
VREF_3
I/O
L23N_3
I/O
L24P_3
L
GND
VCCO_
I/O
LEFT ^L01N_6
VRP_6
I/O
I/O
I/O
L20N_3 L22P_3 L22N_3
I/O
M L01P_6
VRN_6
N M0
I/O
M1
GND
L27N_5 VCCAUX
VREF_5
I/O
L01P_5
CS_B
VCCO_
BOTTOM
I/O
L28P_5
D7
VCCINT
I/O
L31N_5
D4
I/O
L32P_4
GCLK0
I/O
L31N_4
INIT_B
GND
VCCO_
BOTTOM
I/O
L31P_4
DOUT
BUSY
VCCINT
I/O
L30N_4
D2
I/O
L27N_4
DIN
D0
I/O
L27P_4
D1
I/O
L01P_4
VRN_4
GND
VCCO_
RIGHT
I/O
VREF_4
GND
I/O
L01N_3
VRP_3
I/O
L20P_3
I/O
L01P_3
VRN_3
P
M2
I/O
L01N_5
RDWR_B
I/O
L27P_5
I/O
L28N_5
D6
I/O
L31P_5
D5
I/O
L32P_5
GCLK2
I/O
L32N_5
GCLK3
I/O
L32N_4
GCLK1
I/O
L30P_4
D3
VCCAUX
VCCO_
BOTTOM
I/O
L01N_4
VRP_4
DONE
CCLK
Bank 5
Bank 4
VCCO_BOTTOM for Bottom Edge Outputs
DS099-4_17_011005
Figure 45: CP132 Package Footprint (Top View). Note pin 1 indicator in top-left corner and logo orientation.
44 I/O: Unrestricted, general-purpose user I/O
14
DCI: User I/O or reference resistor input for
bank
7 CONFIG: Dedicated configuration pins
12
DUAL: Configuration pin, then possible
user I/O
8
GCLK: User I/O, input, or global buffer
input
11
VREF: User I/O or input voltage reference for
bank
12 VCCO: Output voltage supply for bank
4 JTAG: Dedicated JTAG port pins
4 VCCINT: Internal core voltage supply (+1.2V)
0 N.C.: No unconnected pins in this package 12 GND: Ground
4 VCCAUX: Auxiliary voltage supply (+2.5V)
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
140