XC3S2000-5FGG456C Datasheet, PDF (29/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
The product of w and n yields the total block RAM capacity. Equation 1 and Equation 2 show that as the data bus width
increases, the number of address lines along with the number of addressable memory locations decreases. Using the
permissible DI/DO bus widths as inputs to these equations provides the bus width and memory capacity measures shown
in Table 14.
Table 14: Port Aspect Ratios for Port A or B
DI/DO Bus Width
(w – p Bits)
DIP/DOP
Bus Width (p Bits)
Total Data Path
Width (w Bits)
1
0
1
2
0
2
4
0
4
8
1
9
16
2
18
32
4
36
ADDR Bus Width
(r Bits)
14
13
12
11
10
9
No. of Addressable Block RAM
Locations (n) Capacity (Bits)
16,384
16,384
8,192
16,384
4,096
16,384
2,048
18,432
1,024
18,432
512
18,432
Block RAM Data Operations
Writing data to and accessing data from the block RAM are synchronous operations that take place independently on each
of the two ports.
The waveforms for the write operation are shown in the top half of the Figure 15, Figure 16, and Figure 17. When the WE
and EN signals enable the active edge of CLK, data at the DI input bus is written to the block RAM location addressed by the
ADDR lines.
There are a number of different conditions under which data can be accessed at the DO outputs. Basic data access always
occurs when the WE input is inactive. Under this condition, data stored in the memory location addressed by the ADDR lines
passes through a transparent output latch to the DO outputs. The timing for basic data access is shown in the portions of
Figure 15, Figure 16, and Figure 17 during which WE is Low.
X-Ref Target - Figure 15
CLK
WE
DI
ADDR
DO
0000
XXXX
1111
2222
aa
bb
cc
MEM(aa)
1111
2222
XXXX
dd
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS099-2_14_091410
Figure 15: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Data can also be accessed on the DO outputs when asserting the WE input. This is accomplished using two different
attributes:
Choosing the WRITE_FIRST attribute, data is written to the addressed memory location on an enabled active CLK edge and
is also passed to the DO outputs. WRITE_FIRST timing is shown in the portion of Figure 15 during which WE is High.
Choosing the READ_FIRST attribute, data already stored in the addressed location pass to the DO outputs before that
location is overwritten with new data from the DI inputs on an enabled active CLK edge. READ_FIRST timing is shown in the
portion of Figure 16 during which WE is High.
DS099 (v3.1) June 27, 2013
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Product Specification
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