XC3S2000-5FGG456C Datasheet, PDF (38/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
The output frequency (f_CLKFX) can be expressed as a function of the incoming clock frequency (f_CLKIN) as follows:
f_CLKFX = f_CLKIN(CLKFX_MULTIPLY/CLKFX_DIVIDE)
Equation 3
Regarding the two attributes, it is possible to assign any combination of integer values, provided that two conditions are met:
• The two values fall within their corresponding ranges, as specified in Table 18.
• The f_CLKFX frequency calculated from the above expression accords with the DCM’s operating frequency
specifications.
For example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, then the frequency of the output clock signal would be 5/3
that of the input clock signal.
DFS Frequency Modes
The DFS supports two operating modes, High Frequency and Low Frequency, with each specified over a different clock
frequency range. The DFS_FREQUENCY_MODE attribute chooses between the two modes. When the attribute is set to
LOW, the Low Frequency mode permits the two DFS outputs to operate over a low-to-moderate frequency range. When the
attribute is set to HIGH, the High Frequency mode allows both these outputs to operate at the highest possible frequencies.
DFS With or Without the DLL
The DFS component can be used with or without the DLL component:
Without the DLL, the DFS component multiplies or divides the CLKIN signal frequency according to the respective
CLKFX_MULTIPLY and CLKFX_DIVIDE values, generating a clock with the new target frequency on the CLKFX and
CLKFX180 outputs. Though classified as belonging to the DLL component, the CLKIN input is shared with the DFS
component. This case does not employ feedback loop; therefore, it cannot correct for clock distribution delay.
With the DLL, the DFS operates as described in the preceding case, only with the additional benefit of eliminating the clock
distribution delay. In this case, a feedback loop from the CLK0 output to the CLKFB input must be present.
The DLL and DFS components work together to achieve this phase correction as follows: Given values for the
CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, the DLL selects the delay element for which the output clock edge
coincides with the input clock edge whenever mathematically possible. For example, when CLKFX_MULTIPLY = 5 and
CLKFX_DIVIDE = 3, the input and output clock edges will coincide every three input periods, which is equivalent in time to
five output periods.
Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values achieve faster lock times. With no factors common to the two
attributes, alignment will occur once with every number of cycles equal to the CLKFX_DIVIDE value. Therefore, it is
recommended that the user reduce these values by factoring wherever possible. For example, given CLKFX_MULTIPLY = 9
and CLKFX_DIVIDE = 6, removing a factor of three yields CLKFX_MULTIPLY = 3 and CLKFX_DIVIDE = 2. While both
value-pairs will result in the multiplication of clock frequency by 3/2, the latter value-pair will enable the DLL to lock more
quickly.
Table 18: DFS Attributes
Attribute
DFS_FREQUENCY_MODE
CLKFX_MULTIPLY
CLKFX_DIVIDE
Description
Chooses between High Frequency and Low Frequency modes
Frequency multiplier constant
Frequency divisor constant
Values
Low, High
Integer from 2 to 32
Integer from 1 to 32
Table 19: DFS Signals
Signal Direction
Description
CLKFX
Output
Multiplies the CLKIN frequency by the attribute-value ratio (CLKFX_MULTIPLY/CLKFX_DIVIDE) to
generate a clock signal with a new target frequency.
CLKFX180
Output Generates a clock signal with same frequency as CLKFX, only shifted 180° out-of-phase.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
38