XC3S2000-5FGG456C Datasheet, PDF (118/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Once the FPGA enters User mode after completing configuration, the DONE pin no longer drives the DONE pin Low. The
bitstream generator option DonePin determines whether or not a pull-up resistor is present on the DONE pin to pull the pin
to VCCAUX. If the pull-up resistor is eliminated, then the DONE pin must be pulled High using an external pull-up resistor or
one of the FPGAs in the design must actively drive the DONE pin High via the DriveDone bitstream generator option.
The bitstream generator option DriveDone causes the FPGA to actively drive the DONE output High after configuration. This
option should only be used in single-FPGA designs or on the last FPGA in a multi-FPGA daisy-chain.
By default, the bitstream generator software retains the pull-up resistor and does not actively drive the DONE pin as
highlighted in Table 74, which shows the interaction of these bitstream options in single- and multi-FPGA designs.
Table 74: DonePin and DriveDone Bitstream Option Interaction
DonePin DriveDone
Single- or Multi-
FPGA Design
Comments
Pullnone
No
Single
External pull-up resistor, with value between 330Ω to 3.3kΩ, required on DONE.
Pullnone
No
Multi
External pull-up resistor, with value between 330Ω to 3.3kΩ, required on common
node connecting to all DONE pins.
Pullnone
Yes
Single
OK, no external requirements.
Pullnone
Yes
Multi
DriveDone on last device in daisy-chain only. No external requirements.
Pullup
No
Single
OK, but pull-up on DONE pin has slow rise time. May require 330Ω pull-up resistor
for high CCLK frequencies.
Pullup
No
Multi
External pull-up resistor, with value between 330Ω to 3.3kΩ, required on common
node connecting to all DONE pins.
Pullup
Yes
Single
OK, no external requirements.
Pullup
Yes
Multi
DriveDone on last device in daisy-chain only. No external requirements.
M2, M1, M0: Configuration Mode Selection
The M2, M1, and M0 inputs select the FPGA configuration mode, as described in Table 75. The logic levels applied to the
mode pins are sampled on the rising edge of INIT_B.
Table 75: Spartan-3 FPGA Mode Select Settings
Configuration Mode
Master Serial
Slave Serial
Master Parallel
Slave Parallel
JTAG
Reserved
Reserved
Reserved
After Configuration
M2
M1
M0
0
0
0
1
1
1
0
1
1
1
1
0
1
0
1
0
0
1
0
1
0
1
0
0
X
X
X
Notes:
1. X = don’t care, either 0 or 1.
Before and during configuration, the mode pins have an internal pull-up resistor to VCCAUX, regardless of the HSWAP_EN
pin. If the mode pins are unconnected, then the FPGA defaults to the Slave Serial configuration mode. After configuration
successfully completes, any levels applied to these input are ignored. Furthermore, the bitstream generator options M0Pin,
M1Pin, and M2Pin determines whether a pull-up resistor, pull-down resistor, or no resistor is present on its respective mode
pin, M0, M1, or M2.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
118