XC3S2000-5FGG456C Datasheet, PDF (101/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 38
PROG_B
(Input)
INIT_B
(Open-Drain)
CS_B
(Input)
RDWR_B
(Input)
CCLK
(Input/Output)
D0 - D7
(Inputs)
BUSY
(Output)
T_SMCCW
T_SMCSCC
T_CCH
T_SMCCCS
T_CCL
T_SMWCC
T_SMDCC
T_SMCCD
1/F_CCPAR
High-Z
Byte 0
Byte 1
T_SMCKBY
Byte n
T_SMCKBY
Byte n+1
BUSY
High-Z
Figure 38: Waveforms for Master and Slave Parallel Configuration
DS099-3_05_041103
Table 67: Timing for the Master and Slave Parallel Configuration Modes
Symbol
Description
Clock-to-Output Times
T_SMCKBY
The time from the rising transition on the CCLK pin to a signal transition at
the BUSY pin
Setup Times
T_SMDCC
The time from the setup of data at the D0-D7 pins to the rising transition at
the CCLK pin
T_SMCSCC
T_SMCCW(3)
The time from the setup of a logic level at the CS_B pin to the rising
transition at the CCLK pin
The time from the setup of a logic level at the RDWR_B pin to the rising
transition at the CCLK pin
Hold Times
T_SMCCD
The time from the rising transition at the CCLK pin to the point when data
is last held at the D0-D7 pins
T_SMCCCS
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the CS_B pin
T_SMWCC(3)
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the RDWR_B pin
Slave/
Master
Slave
Both
Both
All Speed Grades
Units
Min
Max
–
12.0
ns
10.0
–
ns
10.0
–
ns
10.0
–
ns
0
–
ns
0
–
ns
0
–
ns
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
101