XC3S2000-5FGG456C Datasheet, PDF (115/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Table 72: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes (Cont’d)
Pin Name Direction
Description
BUSY
Output
Configuration Data Rate Control for Parallel Mode:
In the Slave and Master Parallel modes, BUSY throttles the rate at which configuration data is loaded.
BUSY is only necessary if CCLK operates at greater than 50 MHz. Ignore BUSY for frequencies of 50
MHz and below.
When BUSY is Low, the FPGA accepts the next configuration data byte on the next rising CCLK edge for
which CS_B and RDWR_B are Low. When BUSY is High, the FPGA ignores the next configuration data
byte. The next configuration data value must be held or reloaded until the next rising CCLK edge when
BUSY is Low. When CS_B is High, BUSY is in a high impedance state.
INIT_B
Bidirectional
(open-drain)
BUSY
Function
0
The FPGA is ready to accept the next configuration data byte.
1
The FPGA is busy processing the current configuration data byte and is not
ready to accept the next byte.
Hi-Z
If CS_B is High, then BUSY is high impedance.
This signal is located in Bank 4 and its output voltage is determined by VCCO_4. The BitGen option
Persist permits this pin to retain its configuration function in the User mode.
Initializing Configuration Memory/Configuration Error (active-Low):
See description under Serial Configuration Modes, page 112.
JTAG Configuration Mode
In the JTAG configuration mode all dual-purpose configuration pins are unused and behave exactly like user-I/O pins, as
shown in Table 79. See Table 75 for Mode Select pin settings required for JTAG mode.
Dual-Purpose Pin I/O Standard During Configuration
During configuration, the dual-purpose pins default to CMOS input and output levels for the associated VCCO voltage
supply pins. For example, in the Parallel configuration modes, both VCCO_4 and VCCO_5 are required. If connected to
+2.5V, then the associated pins conform to the LVCMOS25 I/O standard. If connected to +3.3V, then the pins drive LVCMOS
output levels and accept either LVTTL or LVCMOS input levels.
Dual-Purpose Pin Behavior After Configuration
After the configuration process completes, these pins, if they were borrowed during configuration, become user-I/O pins
available to the application. If a dual-purpose configuration pin is not used during the configuration process—i.e., the parallel
configuration pins when using serial mode—then the pin behaves exactly like a general-purpose I/O. See I/O Type:
Unrestricted, General-purpose I/O Pins section.
DCI: User I/O or Digitally Controlled Impedance Resistor Reference Input
These pins are individual user-I/O pins unless one of the I/O standards used in the bank requires the Digitally Controlled
Impedance (DCI) feature. If DCI is used, then 1% precision resistors connected to the VRP_# and VRN_# pins match the
impedance on the input or output buffers of the I/O standards that use DCI within the bank. The ‘#’ character in the pin name
indicates the associated I/O bank and is an integer, 0 through 7.
There are two DCI pins per I/O bank, except in the CP132 and TQ144 packages, which do not have any DCI inputs for
Bank 5.
VRP and VRN Impedance Resistor Reference Inputs
The 1% precision impedance-matching resistor attached to the VRP_# pin controls the pull-up impedance of PMOS
transistor in the input or output buffer. Consequently, the VRP_# pin must connect to ground. The ‘P’ character in “VRP”
indicates that this pin controls the I/O buffer’s PMOS transistor impedance. The VRP_# pin is used for both single and split
termination.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
115