XC3S2000-5FGG456C Datasheet, PDF (107/272 Pages) Xilinx, Inc – Introduction and Ordering Information

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Spartan-3 FPGA Family:
Pinout Descriptions
Product Specification
Introduction
This data sheet module describes the various pins on a Spartan®-3 FPGA and how they connect to the supported
component packages.
• The Pin Types section categorizes all of the FPGA pins by their function type.
• The Pin Definitions section provides a top-level description for each pin on the device.
• The Detailed, Functional Pin Descriptions section offers significantly more detail about each pin, especially for the dual-
or special-function pins used during device configuration.
• Some pins have associated behavior that is controlled by settings in the configuration bitstream. These options are
described in the Bitstream Options section.
• The Package Overview section describes the various packaging options available for Spartan-3 FPGAs. Detailed pin
list tables and footprint diagrams are provided for each package solution.
Pin Descriptions
Pin Types
A majority of the pins on a Spartan-3 FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12
different functional types of pins on Spartan-3 device packages, as outlined in Table 69. In the package footprint drawings
that follow, the individual pins are color-coded according to pin type as in the table.
Table 69: Types of Pins on Spartan-3 FPGAs
Pin Type/
Color Code
Description
Pin Name
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to IO,
form differential I/Os.
IO_Lxxy_#
DUAL
Dual-purpose pin used in some configuration modes during the configuration
process and then usually available as a user I/O after configuration. If the pin is not
used during configuration, this pin behaves as an I/O-type pin. There are 12
dual-purpose configuration pins on every package. The INIT_B pin has an internal
pull-up resistor to VCCO_4 or VCCO_BOTTOM during configuration.
IO_Lxxy_#/DIN/D0, IO_Lxxy_#/D1,
IO_Lxxy_#/D2, IO_Lxxy_#/D3,
IO_Lxxy_#/D4, IO_Lxxy_#/D5,
IO_Lxxy_#/D6, IO_Lxxy_#/D7,
IO_Lxxy_#/CS_B,
IO_Lxxy_#/RDWR_B,
IO_Lxxy_#/BUSY/DOUT,
IO_Lxxy_#/INIT_B
CONFIG
Dedicated configuration pin. Not available as a user-I/O pin. Every package has CCLK, DONE, M2, M1, M0,
seven dedicated configuration pins. These pins are powered by VCCAUX and have PROG_B, HSWAP_EN
a dedicated internal pull-up resistor to VCCAUX during configuration.
JTAG
Dedicated JTAG pin. Not available as a user-I/O pin. Every package has four
TDI, TMS, TCK, TDO
dedicated JTAG pins. These pins are powered by VCCAUX and have a dedicated
internal pull-up resistor to VCCAUX during configuration.
DCI
Dual-purpose pin that is either a user-I/O pin or used to calibrate output buffer
IO/VRN_#
impedance for a specific bank using Digital Controlled Impedance (DCI). There are IO_Lxxy_#/VRN_#
two DCI pins per I/O bank.
IO/VRP_#
IO_Lxxy_#/VRP_#
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Product Specification
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