XC3S2000-5FGG456C Datasheet, PDF (11/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 7
T
T1
TCE
T2
TFF1
D
Q
CE
CK
SR REV
DDR
MUX
D
Q
TFF2
CE
CK
SR REV
Three-state Path
O1
OTCLK1
OCE
O2
OTCLK2
I
IQ1
ICLK1
ICE
IQ2
ICLK2
SR
REV
OFF1
D
Q
CE
CK
SR REV
DDR
MUX
D
Q
OFF2
CE
CK
SR REV
Program-
mable
Output
DCI
Driver
Output Path
VCCO
Pull-Up
Pull-
Down
ESD
I/O
Pin
ESD
Keeper
Latch
D
Q
IFF1
CE
CK
SR REV
D
Q
IFF2
CE
CK
SR REV
Fixed
Delay
Fixed
Delay
LVCMOS, LVTTL, PCI
Single-ended Standards
using VREF
Differential Standards
VREF
Pin
I/O Pin
from
Adjacent
IOB
Input Path
Note: All IOB signals originating from the FPGA's internal logic have an optional polarity inverter.
Figure 7: Simplified IOB Diagram
DS099-2_01_091410
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
11