DS632 Datasheet, PDF (9/17 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

XPS Mailbox (v2.00a)
Table 5: XPS Mailbox Parameter-Port Dependencies
Generic
or Port
Name
Affects Depends Relationship Description
Design Parameters
G6 C_SPLB<x>_DWIDTH
P7, P10, P33
-
Affects the number of bits in data bus
This value is calculated as:
G8 C_SPLB<x>_MID_WIDTH
P5
G9
log₂(C_SPLB<x>_NUM_MASTERS)
with a minimum value of 1
G9
C_SPLB<x>_NUM_MASTER
S
P36, P37,
P38, P42
-
Affects the number of PLB masters
G14 C_FSL_DWIDTH
P44, P49
-
Affects the number of bits in data bus
I/O Signals
P5
PLB<x>_masterID[0:
C_SPLB_MID_WIDTH - 1]
-
Width of the PLB<x>_masterID
G8
varies according to
C_SPLB<x>_MID_WIDTH
P7
PLB<x>_BE[0:
(C_SPLB_DWIDTH/8) -1]
-
G6
Width of the PLB<x>_BE varies
according to C_SPLB<x>_DWIDTH
P10
PLB<x>_wrDBus[0:
C_SPLB_DWIDTH - 1]
-
G6
Width of the PLB<x>_wrDBus varies
according to C_SPLB<x>_DWIDTH
P33
Sl<x>_rdDBus[0:
C_SPLB_DWIDTH - 1]
-
G6
Width of the Sl<x>_rdDBus varies
according to C_SPLB<x>_DWIDTH
Sl<x>_MBusy[0:
P36 C_SPLB_NUM_MASTERS -
-
1]
Width of the Sl<x>_MBusy varies
G9
according to
C_SPLB<x>_NUM_MASTERS
Sl<x>_MWrErr[0:
P37 C_SPLB_NUM_MASTERS -
-
1]
Width of the Sl<x>_MWrErr varies
G9
according to
C_SPLB<x>_NUM_MASTERS
Sl<x>_MRdErr[0:
P38 C_SPLB_NUM_MASTERS -
-
1]
Width of the Sl<x>_MRdErr varies
G9
according to
C_SPLB<x>_NUM_MASTERS
Sl<x>_MIRQ[0:
P42 C_SPLB_NUM_MASTERS -
-
1]
Width of the Sl<x>_MIRQ varies
G9
according to
C_SPLB<x>_NUM_MASTERS
P44 FSL<x>_M_Data
G14
Width of the FSL<x>_M_Data varies
according to C_FSL_DWIDTH
P49 FSL<x>_S_Data
G14
Width of the FSL<x>_S_Data varies
according to C_FSL_DWIDTH
DS632 June 24, 2009
www.xilinx.com
9
Product Specification