DS632 Datasheet, PDF (5/17 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

XPS Mailbox (v2.00a)
Table 2: XPS Mailbox FSL I/O Signal Description
Port
Signal Name
Interface I/O
Initial
State
FSL Master Interface Signals
P43 FSL<x>_M_Clk
MFSL
I
N/A
P44 FSL<x>_M_Data
P45 FSL<x>_M_Control
P46 FSL<x>_M_Write
MFSL
I
0
MFSL
I
0
MFSL
I
0
P47 FSL<x>_M_Full
MFSL
O
N/A
FSL Slave Interface Signals
P48 FSL<x>_S_Clk
SFSL
I
N/A
P49 FSL<x>_S_Data
P50 FSL<x>_S_Control
P51 FSL<x>_S_Read
P52 FSL<x>_S_Exists
SFSL
O
N/A
SFSL
O
N/A
SFSL
I
0
SFSL
O
N/A
Description
This port provides the input clock
to the FSL master interface of
the mailbox when used in the
asynchronous FIFO mode
(C_ASYNC_CLKS = 1). All
transactions on the master
interface use this clock when
implemented in the
asynchronous mode
The data input to the FSL master
interface of the mailbox
Unused for mailbox
Input signal that controls the
write enable signal of the FSL
master interface of the FIFO.
When set to 1, the value of
FSL<x>_M_Data is pushed into
the mailbox FIFO on a rising
clock edge.
Output signal on the FSL master
interface of the FIFO indicating
that the FIFO is full.
This port provides the input clock
to the FSL slave interface on the
mailbox when used in the
asynchronous FIFO mode
(C_ASYNC_CLKS = 1). All
transactions on the slave
interface use this clock when
implemented in the
asynchronous mode
The data output bus onto the
FSL slave interface of the
mailbox
Unused for mailbox
Input signal on the FSL slave
interface that controls the read
acknowledge signal of the FIFO.
When set to 1, the value of
FSL<x>_S_Data is popped from
the FIFO on a rising clock edge.
Output signal on the FSL slave
interface indicating that FIFO
contains valid data.
DS632 June 24, 2009
www.xilinx.com
5
Product Specification