DS632 Datasheet, PDF (16/17 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

XPS Mailbox (v2.00a)
Table 24: XPS Mailbox IP Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0 - 28 Reserved
Reserved for future use
Mailbox Error Interrupt Pending status for this interface
29
ERR
Read
’0’
’0’ = No pending interrupt
’1’ = Pending interrupt for Mailbox errors
Mailbox Receive Threshold Interrupt Pending status for this
30
RTI
Read
’0’
interface
’0’ = No pending interrupt
’1’ = Pending interrupt for data level in receive FIFO
Mailbox Send Threshold Interrupt Pending status for this
interface
31
STI
Read
’0’
’0’ = No pending interrupt
’1’ = Pending interrupt for data level in send FIFO
Design Implementation
Target Technology
The intended target technology is an FPGA in one of the following families: Spartan-3, Spartan-3E,
Spartan-3A, Spartan-3A DSP, Automotive Spartan-3/3A/3E/3A DSP, Virtex-4, Virtex-4QV, Virtex-4Q,
Virtex-5, Virtex-6.
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Reference Documents
1. IBM CoreConnect 128-Bit Processor Local Bus, Architectural Specification (v4.6).
Revision History
Date
08/31/2007
4/24/09
6/26/09
Version
1.0
1.1
1.2
Revision
Initial Xilinx release.
Replaced references to supported device families and tool name(s) with hyperlink to
PDF file.
Updated for EDK_L 11.2; created v2.00a.
16
www.xilinx.com
DS632 June 24, 2009
Product Specification