DS632 Datasheet, PDF (7/17 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

XPS Mailbox (v2.00a)
Table 4: XPS Mailbox Design Parameters
Generic Feature/Description Parameter Name Allowable Values
System Parameter
G1
Target FPGA family
C_FAMILY
spartan3, aspartan3,
spartan3e,
aspartan3e,
spartan3a,
aspartan3a,
spartan3adsp,
aspartan3adsp,
spartan6, virtex4,
qrvirtex4, qvirtex4,
virtex5, virtex6
G2
Level of external reset
C_EXT_RESET_HI
GH
0 or 1
PLB Parameters
G3
PLB Base Address
C_SPLB<x>_BASE
ADDR
Valid Address[1]
G4
PLB High Address
C_SPLB<x>_HIGHA
DDR
Valid Address[2]
G5
PLB least significant
address bus width
C_SPLB<x>_AWIDT
H
32
G6
PLB data width
C_SPLB<x>_DWIDT
H
32, 64, 128
0 = Shared Bus
G7
Selects point-to-point or
shared bus topology
C_SPLB<x>_P2P
Topology
1 = Point-to-Point Bus
Topology^[4]
G8
PLB Master ID Bus Width
C_SPLB<x>_MID_
WIDTH
log₂(C_SPLB_NUM_
MASTERS) with a
minimum value of 1
G9
Number of PLB Masters
C_SPLB<x>_NUM_
MASTERS
1 - 16
G10 Support Bursts
C_SPLB<x>_SUPP
ORT_BURSTS
0
G11
Width of the Slave Data C_SPLB_NATIVE_
Bus
DWIDTH
32
XPS Mailbox Parameters
Specify clocking modes
G12 of FIFO as synchronous C_ASYNC_CLKS
or asynchronous
0-1
G13
Use BRAMs to
implement FIFO
C_IMPL_STYLE
0-1
G14 FSL bus width
C_FSL_DWIDTH
32
Default VHDL
Value Type
virtex-5 string
1
integer
None[3]
std_logic_
vector
None[3]
std_logic_
vector
32
integer
32
integer
0
integer
1
integer
1
integer
0
integer
32
integer
0
Integer
1
Integer
32
Integer
DS632 June 24, 2009
www.xilinx.com
7
Product Specification