DS632 Datasheet, PDF (6/17 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

XPS Mailbox (v2.00a)
Table 3: XPS Mailbox Common I/O Signal Description
Port
Signal Name
Interface I/O
Initial
State
FSL Common Interface Signals
P53 FSL_Clk
I
N/A
P54 SYS_Rst
P55 FSL_Rst
P56 Interrupt_0
P57 Interrupt_1
I
N/A
O
0
Common Signals
O
0
O
0
Description
This is the input clock to the
mailbox when used in
synchronous FIFO mode
(C_ASYNC_CLKS = 0) and both
interfaces are FSL based
(C_INTERFACE_<x>_IS_FSL =
1). The FSL_Clk is in this case
used to clock the core, in all
other cases are the internal
mailbox clock automatically
derived from either
SPLB<x>_Clk and/or
FSL<x>_M_Clk/FSL<x>_S_Clk
depending on the settings.
External system reset. This
signal is only required when both
interfaces are configured to be
FSL interfaces. If any PLB
interface is available this signal is
optional.
Output reset signal generated by
the FSL reset logic. Any
peripherals connected to the
FSL bus may use this reset
signal to operate the peripheral
reset.
Interrupt signal that data is
available at interface 0
Interrupt signal that data is
available at interface 1
XPS Mailbox Design Parameters
To allow the user to obtain a XPS Mailbox that is uniquely tailored for the system, certain features can
be parameterized in the XPS Mailbox design. This allows the user to configure a design that utilizes the
resources required by the system only and that operates with the best possible performance. The fea-
tures that can be parameterized in the XPS Mailbox design are as shown in Table 4. The PLB related
generics, G3 through G10, are separately configured for each interface.
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DS632 June 24, 2009
Product Specification