DS632 Datasheet, PDF (8/17 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

XPS Mailbox (v2.00a)
Table 4: XPS Mailbox Design Parameters (Contd)
Generic Feature/Description Parameter Name
Allowable Values
Default
Value
VHDL
Type
G15
If interface 0 shall use
FSL instead of PLB
C_INTERFACE_0_I
S_FSL
0-1
0
Integer
G16
If interface 1shall use
FSL instead of PLB
C_INTERFACE_1_I
S_FSL
0-1
0
Integer
G17
FIFO depth of mailbox
C_MAILBOX_DEPT
H
16 - 8192
16
Integer
Read Clock period for
G18
interface 0 when
C_READ_CLOCK_P
asynchronous LUTRAM ERIOD_0
> 0 when enabled
is used (in ps)
0
Integer
Read Clock period for
G19
interface 1when
C_READ_CLOCK_P
asynchronous LUTRAM ERIOD_0
> 0 when enabled
is used (in ps)
0
Integer
Notes:
1. The user must set the values. The C_BASEADDR must be a multiple of the range, where the range is
C_HIGHADDR - C_BASEADDR + 1.
2. C_HIGHADDR - C_BASEADDR must be a power of 2 greater than equal to C_BASEADDR + 0x3F.
3. No default value will be specified to insure that the actual value is set, i.e., if the value is not set, a compiler
error will be generated.
4. Value of ’1’ is not supported in this core.
Allowable Parameter Combinations
The address range specified by C_BASEADDR and C_HIGHADDR must be a power of 2, and must be
at least 0x3F.
For example, if C_BASEADDR = 0xE0000000, C_HIGHADDR must be at least = 0xE000003F.
XPS Mailbox Parameter - Port Dependencies
The dependencies between the XPS Mailbox core design parameters and I/O signals are described in
Table 5. In addition, when certain features is deselected, the related logic will no longer be a part of the
design. The unused input and output signals are set to a specified value.
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DS632 June 24, 2009
Product Specification