DS632 Datasheet, PDF (11/17 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

XPS Mailbox (v2.00a)
Table 8: XPS Mailbox Write Data Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0-
C_FSL_DWID
TH - 1
WRDATA
Write
-
Write register to send data to the other inter-
face
XPS Mailbox Read Data Register (RDDATA)
Reading from this register will pop one value from the mail FIFO. Trying to read while the empty flag
is set will result in an error and the EMPTY_ERROR bit will be set. The register is read only and a write
request issued to RDDATA will be ignored. Bit assignment in the RDDATA register is described in
Table 10.
Table 9: Read Data Register
0
RDDATA
C_FSL_DWIDTH-1
Table 10: XPS Mailbox Read Data Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0-
C_FSL_DWID
TH - 1
RDDATA
Read
-
Read register to get data word sent from the
other interface
XPS Mailbox Status Register (STATUS)
The XPS Mailbox Status Register contains the current status of the mailbox. The register is read only
and a write request issued to STATUS will be ignored. Bit assignment in the STATUS register is
described in Table 12
Table 11: Status Register
0
Reserved
RTA
27
28
STA
29
Full Empty
30
31
DS632 June 24, 2009
www.xilinx.com
11
Product Specification