DS632 Datasheet, PDF (2/17 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

XPS Mailbox (v2.00a)
Functional Description
The XPS Mailbox is used for bi-directional inter processor communication. A mailbox is a link between
two otherwise separate processor systems. Other multi-port IP blocks, such as a memory controller etc.,
may also be shared by the two sub systems.
In addition to sending the actual data between processors the mailbox can be used to generate
interrupts between the processors.
The XPS Mailbox in a typical PLBv46 system is shown in the top-level block diagram in Figure 1.
Figure Top x-ref 1
System Number 1
PLBv46 Bus
System Number 2
PLBv46 Bus
Processor
Number 1
Processor
Number 2
Local IPs
for System
Number 1
Mailbox
Local IPs
for System
Number 2
Other
Multiport IPs
DS632_01_020309
Figure 1: XPS Mailbox FPGA in a PLBv46 System
XPS Mailbox I/O Signals
The XPS Mailbox has two interfaces that are used to connect to the rest of the system. Both interfaces
can be independently configured to use FSL or PLBv46. The signal descriptions are included in three
tables:
1. The PLB signals are described inTable 1.
2. The FSL signals are described in Table 2.
3. The common signals are described in Table 3.
All signals in Table 1 and Table 2 apply to both interface sides; <x> denotes the interface number, which
may be 0 or 1.
2
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DS632 June 24, 2009
Product Specification