DS632 Datasheet, PDF (3/17 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

XPS Mailbox (v2.00a)
Table 1: XPS Mailbox PLBv46 I/O Signal Description
Port
Signal Name
Interface I/O
Initial
State
System Signals
P1 SPLB<x>_Clk
System
I
-
P2 SPLB<x>_Rst
System
I
-
PLB Interface Signals
P3 PLB<x>_ABus[0:31]
PLB
I
-
P4 PLB<x>_PAValid
PLB
I
-
P5
PLB<x>_masterID[0:
C_SPLB_MID_WIDTH - 1]
PLB
I
-
P6 PLB<x>_RNW
PLB
I
-
P7
PLB<x>_BE[0:
(C_SPLB_DWIDTH/8) - 1]
PLB
I
-
P8 PLB<x>_size[0:3]
PLB
I
-
P9 PLB<x>_type[0:2]
PLB
I
-
P10
PLB<x>_wrDBus[0:
C_SPLB_DWIDTH - 1]
PLB
I
-
Unused PLB Interface Signals
P11 PLB<x>_UABus[0:31]
PLB
I
-
P12 PLB<x>_SAValid
PLB
I
-
P13 PLB<x>_rdPrim
PLB
I
-
P14 PLB<x>_wrPrim
P15 PLB<x>_abort
P16 PLB<x>_busLock
P17 PLB<x>_MSize[0:1]
P18 PLB<x>_lockErr
P19 PLB<x>_wrBurst
P20 PLB<x>_rdBurst
P21 PLB<x>_wrPendReq
P22 PLB<x>_rdPendReq
P23 PLB<x>_wrPendPri[0:1]
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
P24 PLB<x>_rdPendPri[0:1]
P25 PLB<x>_reqPri[0:1]
P26 PLB<x>_TAttribute[0:15]
PLB
I
-
PLB
I
-
PLB
I
-
Description
PLB clock
PLB reset, active high
PLB address bus
PLB primary address valid
PLB current master identifier
PLB read not write
PLB byte enables
PLB size of requested transfer
PLB transfer type
PLB write data bus
PLB upper address bits
PLB secondary address valid
PLB secondary to primary read
request indicator
PLB secondary to primary write
request indicator
PLB abort bus request
PLB bus lock
PLB data bus width indicator
PLB lock error
PLB burst write transfer
PLB burst read transfer
PLB pending bus write request
PLB pending bus read request
PLB pending write request
priority
PLB pending read request
priority
PLB current request priority
PLB transfer attribute
DS632 June 24, 2009
www.xilinx.com
3
Product Specification