DS632 Datasheet, PDF (12/17 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

XPS Mailbox (v2.00a)
Table 12: XPS Mailbox Status Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0 - 27
Reserved
Reserved for future use
Receive Threshold Active indicates the
current FIFO status of this interface in the
receive direction
28
RTA
Read
0
’0’ = The receive FIFO level is less than or
equal to the RIT threshold
’1’ = The receive FIFO level is greater than the
RIT threshold
Send Threshold Active indicates the current
FIFO status of this interface in the send
direction
29
STA
Read
0
’0’ = The send FIFO level is greater than the
SIT threshold
’1’ = The send FIFO level is less than or equal
to the SIT threshold
Indicates the current status of this interface in
the send direction
30
Full
Read
’0’
’0’ = There is room for more data
’1’ = The FIFO is full, any attempts to write
data will be ignored and generate an error
Indicates the current status of this interface in
the receive direction
31
Empty
Read
’1’
’0’ = There is data available
’1’ = The FIFO is empty, any attempts to read
data will be ignored and generate an error
XPS Mailbox Error Register (ERROR)
The XPS Mailbox Error Register contains the error flags for PLB accesses from this interface. The error
register will be cleared at read, this means that all bits are sticky and that they indicate any errors that
occurred since last time the error register was read. The register is read only and a write request issued
to ERROR will be ignored. Bit assignment in the ERROR register is described in Table 14.
Table 13: Error Register
0
Reserved
Full Empty
Error Error
29
30
31
12
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DS632 June 24, 2009
Product Specification