DS621 Datasheet, PDF (9/12 Pages) Xilinx, Inc – High-speed memory controller interface

Virtex-5 FPGA Embedded Processor Block with PowerPC 440 Processor (Wrapper)
Table 2: Wrapper Design Parameters (Cont’d)
Feature / Description
Parameter Name
Allowable Values
DMA #0 through DMA #3 transmit channel
control (initial value of TX Channel Control
Register)
C_DMA0_TXCHANNEL
CTRL[0:31]
through
C_DMA3_TXCHANNEL
CTRL[0:31]
See Note ⁽⁴⁾.
DMA #0 through DMA #3 receive channel
control (initial value of RX Channel Control
Register)
C_DMA0_RX
CHANNELCTRL[0:31]
through
C_DMA3_RXCHANNEL
CTRL[0:31]
See Note ⁽⁴⁾.
DMA #0 through DMA #3 control register
(bits 2:7 set the initial value of DMA Control
Register bits 26:31)
C_DMA0_CONTROL[0:
7] through
C_DMA3_
CONTROL[0:7]
See Note ⁽⁴⁾.
DMA #0 through DMA #3 Transmit IRQ
coalescing clock divider ratio
C_DMA0_TXIRQ
TIMER[0:9]
through
C_DMA3_TXIRQ
TIMER[0:9]
0b0000000000 =
divide-by-1, through
0b1111111111 =
divide-by-1024
DMA #0 through DMA #3 Receive IRQ
coalescing clock divider ratio
C_DMA0_RXIRQ
TIMER[0:9]
through
C_DMA0_RXIRQ
TIMER[0:9]
0b0000000000 =
divide-by-1, through
0b1111111111 =
divide-by-1024
DCR Interface
Enable the auto-lock feature for the DCR
indirect mode
C_DCR_AUTOLOCK_ _0-1
ENABLE
Synchronization mode for the external
MDCR interface
C_PPCDM_
ASYNCMODE
0=Synchronous,
1=Asynchronous
Synchronization mode for the external
SDCR interface
C_PPCDS_ASYNC
MODE
0=Synchronous,
1=Asynchronous
Default Value
0x0101_0000
0x0101_0000
0b0000_0000
0b11_1111_
1111
0b11_1111_
1111
1
0
0
VHDL
Type
bit_
vector
bit_
vector
bit_v
ector
bit_v
ector
bit_
vector
integer
integer
integer
Notes:
1. Default values for base/high address pair are to insure that the parameters are explicitly set by the user. If the user does not
override the default values, the tools will generate an error.
2. These parameters are calculated and automatically assigned by the EDK XPS tools during the system creation process. Values for
these parameters should not be specified by the user.
3. The size of an address range (HIGHADDR - BASEADDR + 1) must be a power of 2, and BASEADDR must be a multiple of that
size.
4. Refer to the description of the corresponding DCR register in the Embedded Processor Block in Virtex-5 FPGAs Reference Guide
(UG200).
5. The five C_PPC440MC_PRIO parameters must have mutually-unique values.
6. The five C_MPLB_PRIO parameters must have mutually-unique values.
7. Point-to-Point mode is not supported on the crossbar MPLB interface.
8. Each SPLB address range (if used) must be minimum 128MB.
9. If the Interconnect-to-PLB clock ratio is > 1:1 and the design uses any of the MBusy outputs on either SPLB interface
(PPCS*PLBMBUSY), then the C_GENERATE_PLB_TIMESPECS parameter should remain enabled. Otherwise, an undetected
timing violation may occur on the MBusy outputs.
10. If parameter C_MPLB_ARB_MODE is set to 1 (round-robin), parameter C_MPLB_READ_PIPE_ENABLE should not be set to 0.
Otherwise, one crossbar master may monopolize the MPLB bus under certain conditions.
DS621 July 5, 2011
www.xilinx.com
9
Product Specification