DS621 Datasheet, PDF (3/12 Pages) Xilinx, Inc – High-speed memory controller interface

Virtex-5 FPGA Embedded Processor Block with PowerPC 440 Processor (Wrapper)
Table 1: Wrapper I/O Signal Exceptions (Cont’d)
Signal Name
Interface
Signal
Direction
Description
TIEC440ICURDTOUCHPLBPRIO
(tie-off)
Input Tied per parameter C_ICU_RD_TOUCH_PLB_PRIO
TIEC440DCURDLDCACHEPLBPRI
O
(tie-off)
Input Tied per parameter C_DCU_RD_LD_CACHE_PLB_PRIO
TIEC440DCURDNONCACHEPLBP
RIO
(tie-off)
Input Tied per parameter C_DCU_RD_NONCACHE_PLB_PRIO
TIEC440DCURDTOUCHPLBPRIO (tie-off)
Input Tied per parameter C_DCU_RD_TOUCH_PLB_PRIO
TIEC440DCURDURGENTPLBPRIO (tie-off)
Input Tied per parameter C_DCU_RD_URGENT_PLB_PRIO
TIEC440DCUWRFLUSHPLBPRIO (tie-off)
Input Tied per parameter C_DCU_WR_FLUSH_PLB_PRIO
TIEC440DCUWRSTOREPLBPRIO (tie-off)
Input Tied per parameter C_DCU_WR_STORE_PLB_PRIO
TIEC440DCUWRURGENTPLBPRI
O
(tie-off)
Input Tied per parameter C_DCU_WR_URGENT_PLB_PRIO
TIEDCRBASEADDR
(tie-off)
Input Tied per parameter C_IDCR_BASEADDR(0 to 1)
TIEC440ERPNRESET
(tie-off)
Input Tied to 0x0
Design Parameters
Table 2 lists all the parameters on the Wrapper. Some are passed directly to the embedded hard block either as
instance attributes or as tie-off input signals. Others are used to modify the connectivity of the wrapper I/O signal
interface.
Table 2: Wrapper Design Parameters
Feature / Description
Parameter Name
Allowable Values Default Value
VHDL
Type
Unique processor ID
C_PIR[28:31]
(any 4-bit value)
0b1111
std_logic_
vector
Reset value for Endian storage byte ordering C_ENDIAN_RESET
0 = Big Endian
1 = Little Endian
0
std_logic
Reset value for user defined storage
attributes: Tattribute[4:7]
C_USER_RESET[0:3] (any 4-bit value)
0b0000
std_logic_
vector
Interrupt mask for crossbar-related
interrupts (initial value of DCR "IMASK")
C_INTERCONNEC_
IMASK[0:31]
See Note ⁽⁴⁾.
0xFFFF_
FFFF
bit_
vector
Arbitration priority for all CPU fetch requests
C_ICU_RD_FETCH_
PLB_PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
std_logic_
vector
Arbitration priority for all speculative CPU
fetch requests
C_ICU_RD_SPEC_
PLB_PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
std_logic_
vector
Arbitration priority for CPU fetch requests
initiated by icbt instructions
C_ICU_RD_TOUCH_
PLB_PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
std_logic_
vector
Arbitration priority for CPU cacheable load
requests
C_DCU_RD_LD_
CACHE_PLB_PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
std_logic_
vector
Arbitration priority for CPU non-cacheable
load requests
C_DCU_RD_NON
CACHE_PLB_PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
std_logic_
vector
DS621 July 5, 2011
www.xilinx.com
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Product Specification