DS621 Datasheet, PDF (2/12 Pages) Xilinx, Inc – High-speed memory controller interface

Virtex-5 FPGA Embedded Processor Block with PowerPC 440 Processor (Wrapper)
Functional Description
The embedded block in Virtex-5 FXT devices contains the PowerPC 440 processor and other modules that allow
system designers to improve the performance and reduce the fabric resource utilization of FPGA designs. To
improve memory access among the processor and other master devices in the system, the embedded block contains
a high bandwidth crossbar switch. The crossbar accepts transfer requests from the processor’s instruction and data
cache units, from 2 slave PLB interfaces and from 4 DMA controllers, all built into the embedded block. These
transfers can be directed, in parallel, to a high-speed memory controller interface and to a PLB master interface.
For a complete description of the Virtex-5 Embedded Block, see the Embedded Processor Block in Virtex-5 FPGAs
Reference Guide (UG200).
The Wrapper provides connectivity of the embedded block to the FPGA fabric with no intervening gate logic or
storage elements. The purpose of the wrapper is to adapt the configuration parameters and some of the I/O signals
of the embedded block for compatibility with the EDK design environment.
I/O Signals
The I/O signals on the Wrapper are the same as on the embedded block, except as listed in Table 1. For details on
the embedded block I/O signals, refer to the Embedded Processor Block in Virtex-5 FPGAs Reference Guide
(UG200).
Table 1: Wrapper I/O Signal Exceptions
Signal Name
Interface
Signal
Direction
Description
PPCMPLBMSIZE [0:1]
MPLB
Output Driven to constant "10" (128-bits)
PPCMPLBUABUS [0:31]
MPLB
Output Driven to all-zeros
PPCS0PLBMIRQ
[0:C_SPLB0_NUM_MASTERS-1]
SPLB0
Output
Driven to all-zeros if C_SPLB0_PROPAGATE_MIRQ = 0
(default);
driven by PPCS0PLBMIRQ [0:3] output of hard block if
C_SPLB0_PROPAGATE_MIRQ = 1
PLBPPCS0UABUS [0:31]
SPLB0
Input Unconnected
PPCS1PLBMIRQ
[0:C_SPLB1_NUM_MASTERS-1]
SPLB1
Output
Driven to all-zeros if C_SPLB1_PROPAGATE_MIRQ = 0
(default);
driven by PPCS1PLBMIRQ [0:3] output of hard block if
C_SPLB1_PROPAGATE_MIRQ = 1
PLBPPCS1UABUS [0:31]
SPLB1
Input Unconnected
SPLB0_Error [0:3]
(debug)
Output Driven by PPCS0PLBMIRQ [0:3] output of hard block
SPLB1_Error [0:3]
(debug)
Output Driven by PPCS1PLBMIRQ [0:3] output of hard block
DBGC440DEBUGHALT
(debug)
Input
OR’ed with inverse of DBGC440DEBUGHALTNEG to
produce processor block DBGC440DEBUGHALT input (’0’ if
unconnected)
DBGC440DEBUGHALTNEG
(debug)
Input
Inverse OR’ed with DBGC440DEBUGHALT to produce
processor block DBGC440DEBUGHALT input (’1’ if
unconnected)
TIEC440ENDIANRESET
(tie-off)
Input Tied per parameter C_ENDIAN_RESET
TIEC440PIR
(tie-off)
Input Tied per parameter C_PIR
TIEC440USERRESET
(tie-off)
Input Tied per parameter C_USER_RESET
TIEC440ICURDFETCHPLBPRIO
(tie-off)
Input Tied per parameter C_ICU_RD_FETCH_PLB_PRIO
TIEC440ICURDSPECPLBPRIO
(tie-off)
Input Tied per parameter C_ICU_RD_SPEC_PLB_PRIO
DS621 July 5, 2011
www.xilinx.com
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Product Specification