DS621 Datasheet, PDF (1/12 Pages) Xilinx, Inc – High-speed memory controller interface

DS621 July 5, 2011
Virtex-5 FPGA Embedded
Processor Block with PowerPC
440 Processor (Wrapper) (v1.01a)
Product Specification
Introduction
This document described the wrapper for the Virtex^®-5
FPGA embedded processor block. For details regarding
the Virtex-5 Embedded Block, see the Embedded
Processor Block in Virtex-5 FPGAs Reference Guide
(UG200).
Features
• PowerPC^® 440x5 dual-issue, superscalar 32-bit
embedded processor developed by IBM
• 32KB instruction cache, 32KB data cache
• Memory Management Unit (MMU)
• Crossbar interconnect with 9 inputs and 2 outputs
(128 bits wide), implemented in hardware
• 128-bit Processor Local Bus (PLB) version 4.6
interfaces
• High-speed memory controller interface
• Auxiliary Processor Unit (APU) controller and
interface for connecting FPU or custom
coprocessor
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family ⁽¹⁾
Virtex-5
Supported User
Interfaces
PLB, DCR
Resources
Not Applicable
Provided with Core
Documentation
Product Specification
Design Files
VHDL
Example Design
Not Provided
Test Bench
Not Provided
Constraints File
Not Provided
Simulation Model
N/A
Tested Design Tools ⁽²⁾
Design Entry
Tools
ISE
Simulation
ModelSim SE/PE, NC sim
Synthesis Tools
XST
Support
Provided by Xilinx, Inc.
Notes:
1. For a listing of supported derivative devices, see the IDS
Embedded Edition Derivative Support.
2. For the supported versions of the tools, see the ISE Design
Suite 13: Release Notes Guide.
© Copyright 2008-2009, 2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, ISE and other designated brands included herein are trademarks of Xilinx in the United States
and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their
respective owners.
DS621 July 5, 2011
www.xilinx.com
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Product Specification