DS621 Datasheet, PDF (7/12 Pages) Xilinx, Inc – High-speed memory controller interface

Virtex-5 FPGA Embedded Processor Block with PowerPC 440 Processor (Wrapper)
Table 2: Wrapper Design Parameters (Cont’d)
Feature / Description
Parameter Name
Allowable Values Default Value
SPLB0 Data bus width (ignored by wrapper) C_SPLB0_DWIDTH
128
See Note ⁽²⁾.
Slave size of SPLB0 on PLB bus (ignored by ^{C_SPLB0_NATIVE_}
wrapper)
DWIDTH
128 (constant)
SPLB0 support for burst transfers (ignored ^C_SPLB0_
by wrapper)
SUPPORT_BURSTS
1 (constant)
Include C_SPLB0_RNG*_MPLB ranges in ^C_SPLB0_USE_
SPLB0 decode
MPLB_ADDR
0 = exclude,
1 = include
Number of valid C_SPLB0_RNG*_MPLB
ranges
C_SPLB0_NUM_
MPLB_ADDR_RNG
0-4
Base address of SPLB0 access to MC
interface (used to derive value of DCR
"TMPL0_PLBS0_MAP")
C_SPLB0_RNG_MC_
BASEADDR[0:31]
See Notes ⁽³⁾ and ⁽⁸⁾.
High address of SPLB0 access to MC
interface (used to derive value of DCR
"TMPL0_PLBS0_MAP")
C_SPLB0_RNG_MC_
HIGHADDR[0:31]
See Notes ⁽³⁾ and ⁽⁸⁾.
Base address of SPLB0 access to MPLB
interface (used to derive value of DCR
"TMPL0_PLBS0_MAP" if
C_SPLB0_USE_MPLB_ADDR = 1)
C_SPLB0_RNG0_MPLB
_BASEADDR[0:31]
through
See Notes ⁽³⁾ and ⁽⁸⁾.
C_SPLB0_RNG3_MPLB
_BASEADDR[0:31]
High address of SPLB0 access to MC
interface (used to derive value of DCR
"TMPL0_PLBS0_MAP" if
C_SPLB0_USE_MPLB_ADDR = 1)
C_SPLB0_RNG0_MPLB
_HIGHADDR[0:31]
through
See Notes ⁽³⁾ and ⁽⁸⁾.
C_SPLB0_RNG3_MPLB
_HIGHADDR[0:31]
Number of masters connected to SPLB0]
Width of MasterID bus on SPLB0
C_SPLB0_NUM_
MASTERS
C_SPLB0_MID_WIDTH
See Note ⁽²⁾.
See Note ⁽²⁾.
Allow locked transfers on SPLB0 (initial
value of DCR "CFG_PLBS0", field
"LOCKXFER")
C_SPLB0_ALLOW_
LOCK_XFER
0 = disallow,
1 = allow
Allow read address pipelining on SPLB0
(initial value of DCR "CFG_PLBS0", field
"RPIPE")
C_SPLB0_READ_
PIPE_ENABLE
0 = disallow,
1 = allow
Propagate MIRQ signals from crossbar onto ^C_SPLB0_
SPLB0 bus
PROPAGATE_MIRQ
0 = disable,
1 = enable
Point-to-Point interconnect mode on SPLB0.
Currently used only to detect whether the C_SPLB0_P2P
SPLB0 interface is connected.
0 = shared bus
1= point-to-point
-1 = unconnected
See Note ⁽²⁾.
SPLB1 Interface
SPLB1 Address bus width (ignored by
wrapper)
C_SPLB1_AWIDTH
32
See Note ⁽²⁾.
SPLB1 Data bus width (ignored by wrapper) C_SPLB1_DWIDTH
128
See Note ⁽²⁾.
128
128
1
0
0
0xFFFF_FFFF
See Note ⁽¹⁾.
0x0000_0000
See Note ⁽¹⁾.
0xFFFF_FFFF
See Note ⁽¹⁾.
0x0000_0000
See Note ⁽¹⁾.
1
1
1
1
0
-1
32
128
VHDL
Type
integer
integer
integer
integer
integer
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
integer
integer
integer
integer
integer
integer
integer
integer
DS621 July 5, 2011
www.xilinx.com
7
Product Specification