DS621 Datasheet, PDF (10/12 Pages) Xilinx, Inc – High-speed memory controller interface

Virtex-5 FPGA Embedded Processor Block with PowerPC 440 Processor (Wrapper)
Table 3: APU Control Register Initialization
Field Name
Control Register Bits
LD/ST Decode Disable
5
UDI Decode Disable
6
Force UDI Non-auton, late confirm
7
FPU Decode Disable
8
FPU Complex Arith. Disable
9
FPU Convert Disable
10
FPU Estimate/Select Disable
11
FPU Single Precision Disable
12
FPU Double Precision Disable
13
FPU FPSCR Disable
14
Force FPU Non-auton, late confirm
15
Store WriteBack OK
16
Ld/St Priv. Op
17
Force Align
20
LE Trap
21
BE Trap
22
FCM Enable
31
C_APU_
CONTROL bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Default
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4: UDI Configuration Register Initialization
Field Name
Control Register Bits
Primary Op-code
0
Extended Op-code
1:11
Privilege Op
12
Ra Enable
13
Rb Enable
14
GPR Write
15
CR Enable
16
CRField[0:2]
18:20
Type
26:27
Wildcard
30
En
31
C_APU_UDI bits
0
1:11
12
13
14
15
16
17:19
20:21
22
23
DS621 July 5, 2011
www.xilinx.com
10
Product Specification