DS621 Datasheet, PDF (8/12 Pages) Xilinx, Inc – High-speed memory controller interface

Virtex-5 FPGA Embedded Processor Block with PowerPC 440 Processor (Wrapper)
Table 2: Wrapper Design Parameters (Cont’d)
Feature / Description
Parameter Name
Allowable Values Default Value
Slave size of SPLB1 on PLB bus (ignored by C_SPLB1_NATIVE_
wrapper)
DWIDTH
128 (constant)
SPLB1 support for burst transfers (ignored
by wrapper)
C_SPLB1_SUPPORT_
BURSTS
1 (constant)
Include C_SPLB1_RNG*_MPLB ranges in ^C_SPLB1_USE_
SPLB1 decode
MPLB_ADDR
0 = exclude,
1 = include
Number of valid C_SPLB1_RNG*_MPLB
ranges
C_SPLB1_NUM_
MPLB_ADDR_RNG
0-4
Base address of SPLB1 access to MC
interface (used to derive value of DCR
"TMPL0_PLBS1_MAP")
C_SPLB1_RNG_MC_
BASEADDR[0:31]
See Notes ⁽³⁾ and ⁽⁸⁾.
High address of SPLB1 access to MC
interface (used to derive value of DCR
"TMPL0_PLBS1_MAP")
C_SPLB1_RNG_MC_
HIGHADDR[0:31]
See Notes ⁽³⁾ and ⁽⁸⁾.
Base address of SPLB1 access to MPLB
interface (used to derive value of DCR
"TMPL0_PLBS1_MAP" if
C_SPLB1_USE_MPLB_ADDR = 1)
C_SPLB1_RNG0_MPLB
_BASEADDR[0:31]
through
See Notes ⁽³⁾, ⁽⁸⁾
C_SPLB1_RNG3_MPLB
_BASEADDR[0:31]
High address of SPLB1 access to MC
interface (used to derive value of DCR
"TMPL0_PLBS1_MAP" if
C_SPLB1_USE_MPLB_ADDR = 1)
C_SPLB1_RNG0_MPLB
_HIGHADDR[0:31]
through
See Notes ⁽³⁾ and ⁽⁸⁾.
C_SPLB1_RNG3_MPLB
_HIGHADDR[0:31]
Number of masters connected to SPLB1]
C_SPLB1_
NUM_MASTERS
1-4
See Note ⁽²⁾.
Width of MasterID bus on SPLB1
C_SPLB1_MID_
WIDTH
See Note ⁽²⁾.
Allow locked transfers on SPLB1 (initial
value of DCR "CFG_PLBS1", field
"LOCKXFER")
C_SPLB1_ALLOW_
LOCK_XFER
0 = disallow,
1 = allow
Allow read address pipelining on SPLB1
(initial value of DCR "CFG_PLBS1", field
"RPIPE")
C_SPLB1_READ_
PIPE_ENABLE
0 = disallow,
1 = allow
Propagate MIRQ signals from crossbar onto C_SPLB1_PROPAGATE 0 = disable,
SPLB1 bus
_MIRQ
1 = enable
Point-to-Point interconnect mode on SPLB1.
Currently used only to detect whether the C_SPLB1_P2P
SPLB1 interface is connected.
0 = shared bus
1= point-to-point
-1 = unconnected
See Note ⁽²⁾.
DMA0 Through DMA3 Interfaces
Number of DMA channels used in the
design. Used to initially set the following
DCR fields:
CFG_PLBS0:DMA0_EN (if P1),
CFG_PLBS0:DMA1_EN (if P2),
C_NUM_DMA
0-4
CFG_PLBS1:DMA2_EN (if P3),
CFG_PLBS1:DMA3_EN (if =4),
128
1
0
0
0xFFFF_FFFF
See Note ⁽¹⁾.
0x0000_0000
See Note ⁽¹⁾.
0xFFFF_FFFF
See Note ⁽¹⁾.
0x0000_0000
See Note ⁽¹⁾.
1
1
1
1
0
-1
0
VHDL
Type
integer
integer
integer
integer
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
integer
integer
integer
integer
integer
integer
integer
DS621 July 5, 2011
www.xilinx.com
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Product Specification