DS621 Datasheet, PDF (11/12 Pages) Xilinx, Inc – High-speed memory controller interface

Virtex-5 FPGA Embedded Processor Block with PowerPC 440 Processor (Wrapper)
Table 5: DCR Fields Initialized to Constant Values
DCR Name
Field
CFG_PLBM, CFG_PLBS0, CFG_PLBS1
LOCK_SESR
CFG_PLBM
XBAR_PRIORITY_ENA
CFG_PLBM
SL_ETERM_MODE
CFG_PLBS0, CFG_PLBS1
ADDRACK_DLY
TMPL_SEL_REG
TMPL1_XBAR_MAP,
TMPL2_XBAR_MAP,
TMPL3_XBAR_MAP
TMPL1_PLBS0_MAP,
TMPL2_PLBS0_MAP,
TMPL3_PLBS0_MAP
TMPL1_PLBS1_MAP,
TMPL2_PLBS1_MAP,
TMPL3_PLBS1_MAP
Value
1
1
0
1
0X3FFFFFFF
0X00000000
0X00000000
0X00000000
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Reference Documents
1. Embedded Processor Block in Virtex-5 FPGAs Reference Guide (UG200)
Revision History
The following table shows the revision history for this document.
Table 6:
Date
Version
Revision
4/7/08
1.0
Initial Xilinx release.
4/24/09
1.1
Replaced references to supported device families and tool name(s) with hyperlink to PDF file.
7/5/11
1.2
Converted to current data sheet template; incorporated CRs 603088 and 473090; corrected
PDF properties; listed supported device and added table notes in LogiCORE Facts Table.
DS621 July 5, 2011
www.xilinx.com
11
Product Specification