DS621 Datasheet, PDF (5/12 Pages) Xilinx, Inc – High-speed memory controller interface

Virtex-5 FPGA Embedded Processor Block with PowerPC 440 Processor (Wrapper)
Table 2: Wrapper Design Parameters (Cont’d)
Feature / Description
Parameter Name
Allowable Values Default Value
High address of the memory connected to
the PowerPC processor 440MC interface.
See ⁽²⁾.
C_PPC440MC_ADDR_
HIGH[0:31]
See Note ⁽²⁾.
Mask used to determine if there is a row
conflict between this transaction and
previous transaction (initial value of DCR
"MI_ROWCONFLICT_MASK")
C_PPC440MC
_ROW_CONFLICT_
MASK[0:31]
Mask used to determine if there is a bank
conflict between this transaction and
previous transaction (initial value of DCR
"MI_BANKCONFLICT_MASK")
C_PPC440MC_
BANK_CONFLICT_
MASK[0:31]
Control and configuration for the memory
controller interface (initial value of DCR
"MI_CONTROL")
C_PPC440MC_
CONTROL[0:31]
[See Note ⁽⁴⁾.
Secondary arbitration priority for all
instruction fetches requested by the CPU for
the MC interface (initial value of DCR
"ARB_XBM", field "440ICUR")
C_PPC440MC_
PRIO_ICU
0-4
See Notes ⁽⁴⁾ and ⁽⁵⁾.
Secondary arbitration priority for all data
writes requested by the CPU for the MC
interface (initial value of DCR "ARB_XBM",
field "440DCUW")
C_PPC440MC_
PRIO_DCUW
0-4
See Notes ⁽⁴⁾ and ⁽⁵⁾.
Secondary arbitration priority for all data
reads requested by the CPU for the MC
interface (initial value of DCR "ARB_XBM",
field "440DCUR")
C_PPC440MC
_PRIO_DCUR
0-4
See Notes ⁽⁴⁾ and ⁽⁵⁾.
Secondary arbitration priority for all
transactions requested by SPLB1, DMA2 or
DMA3 for the MC interface (initial value of
DCR "ARB_XBM", field "PLBS1")
C_PPC440MC_
PRIO_SPLB1
0-4
See Notes ⁽⁴⁾ and ⁽⁵⁾.
Secondary arbitration priority for all
transactions requested by SPLB0, DMA0 or
DMA1 for the MC interface (initial value of
DCR "ARB_XBM", field "PLBS0")
C_PPC440MC_
PRIO_SPLB0
0-4
See Notes ⁽⁴⁾ and ⁽⁵⁾.
MC interface arbitration mode (initial value of ^{C_PPC440MC_ARB_}
DCR "ARB_XBM", field "MODE")
MODE
0 = Least Recently
Used (LRU)
1 = round-robin
2= fixed priority
Maximum number of quad-words per burst
through crossbar to MC interface (used to
derive the initial value of DCR
"CFG_PLBS0" and "CFG_PLBS1", fields
"THRMIB" and "THWMIB")
C_PPC440MC_
MAX_BURST
1, 2, 4, 8, 16
MPLB Interface
MPLB Address bus width (ignored by
wrapper)
C_MPLB_AWIDTH
32
See Note ⁽²⁾.
MPLB Data bus width (ignored by wrapper) C_MPLB_DWIDTH
128
See Note ⁽²⁾.
Master size of MPLB on PLB bus (ignored by C_MPLB_NATIVE_
wrapper)
DWIDTH
128 (constant)
0x00000000
0x00000000
0x00000000
0x0000008f
4
3
2
0
1
0
8
32
128
128
VHDL
Type
std_logic_
vector
bit_
vector
bit_
vector
bit_
vector
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
DS621 July 5, 2011
www.xilinx.com
5
Product Specification