DS621 Datasheet, PDF (4/12 Pages) Xilinx, Inc – High-speed memory controller interface

Virtex-5 FPGA Embedded Processor Block with PowerPC 440 Processor (Wrapper)
Table 2: Wrapper Design Parameters (Cont’d)
Feature / Description
Parameter Name
Allowable Values Default Value
VHDL
Type
Arbitration priority for CPU load requests
initiated by dcbt instructions
C_DCU_RD_TOUCH_
PLB_PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
std_logic_
vector
Arbitration priority for a CPU load request
associated with an "urgent" state in which
two or more CPU data cache operations are
pending, waiting for a previous request to be
serviced
C_DCU_RD_URGENT_
PLB_PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
std_logic_
vector
Arbitration priority for CPU write requests
initiated by flush instructions
C_DCU_WR_FLUSH_
PLB_PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
std_logic_
vector
Arbitration priority for CPU write requests
initiated by store instructions
C_DCU_WR_STORE_
PLB_PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
std_logic_
vector
Arbitration priority for a CPU write request
associated with an "urgent" state in which
two or more CPU data cache operations are
pending, waiting for a previous request to be
serviced
C_DCU_WR_URGENT_
PLB_PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
std_logic_
vector
Arbitration priority for read/write requests
initialed by DMA controller #0 (initial value of
DCR "CFG_PLBS0", field "DMA0_PRI")
C_DMA0_PLB_
PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
bit_
vector
Arbitration priority for read/write requests
initialed by DMA controller #1 (initial value of
DCR "CFG_PLBS0", field "DMA1_PRI")
C_DMA1_PLB_
PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
bit_
vector
Arbitration priority for read/write requests
initialed by DMA controller #2 (initial value of
DCR "CFG_PLBS1", field "DMA2_PRI")
C_DMA2_PLB_
PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
bit_
vector
Arbitration priority for read/write requests
initialed by DMA controller #3 (initial value of
DCR "CFG_PLBS1", field "DMA3_PRI")
C_DMA3_PLB_
PRIO[0:1]
0b00 = lowest
through
0b11 = highest
0b00
bit_
vector
Base address (word-aligned) of DCR
C_IDCR_
register block internal to the embedded block _{BASEADDR[0:9]}
0b00_0000_0000,
0b01_0000_0000,
0b10_0000_0000,
0b11_0000_0000
0b11_1111_111
1
std_logic_
See Note ⁽¹⁾.
vector
High address of DCR register block internal C_IDCR_
to the embedded block
HIGHADDR[0:9]
C_IDCR_BASEADD
R+
0b00_1111_1111
0b00_0000_000
0
See Note ⁽¹⁾.
std_logic_
vector
Enables generation of timing constraints for
proper synchronization of SPLB MBusy
output signals to the PLB clock. See Note ⁽⁹⁾.
C_GENERATE_PLB_
TIMESPECS
0 = disable
1 = enable
1
integer
APU Controller
Initializes 17 of the bits of the APU Control ^C_APU_
DCR. See Table 3.
CONTROL[0:16]
0b00010000000
000000
bit_
vector
Initializes 24 of the bits of UDI #0 through
UDI #15 configuration register. See Table 4.
C_APU_UDI_0[0:23]
through
C_APU_UDI_15[0:23]
0x000000
bit_
vector
Memory Controller Interface
Base address of the memory connected to C_PPC440MC_ADDR_
the PowerPC 440 Processor MC interface BASE[0:31]
See Note ⁽²⁾.
0xFFFFFFFF
std_logic_
vector
DS621 July 5, 2011
www.xilinx.com
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Product Specification