DS621 Datasheet, PDF (6/12 Pages) Xilinx, Inc – High-speed memory controller interface

Virtex-5 FPGA Embedded Processor Block with PowerPC 440 Processor (Wrapper)
Table 2: Wrapper Design Parameters (Cont’d)
Feature / Description
Parameter Name
Allowable Values Default Value
Secondary arbitration priority for all
instruction fetches requested by the CPU for
the MPLB interface (initial value of DCR
C_MPLB_PRIO_ICU
0-4
See Notes ⁽⁴⁾ and ⁽⁶⁾.
4
"ARB_XBC", field "440ICUR")
Secondary arbitration priority for all data
writes requested by the CPU for the MPLB C_MPLB_PRIO_
interface (initial value of DCR "ARB_XBC", _DCUW
0-4
See Notes ⁽⁴⁾ and ⁽⁶⁾.
3
field "440DCUW")
Secondary arbitration priority for all data
reads requested by the CPU for the MPLB ^C_MPLB_PRIO_
interface (initial value of DCR "ARB_XBC", DCUR
0-4
See Notes ⁽⁴⁾ and ⁽⁶⁾.
2
field "440DCUR")
Secondary arbitration priority for all
transactions requested by SPLB1, DMA2 or ^C_MPLB_PRIO_
DMA3 for the MPLB interface (initial value of _SPLB1
0-4
See Notes ⁽⁴⁾ and ⁽⁶⁾.
0
DCR "ARB_XBC", field "PLBS1")
Secondary arbitration priority for all
transactions requested by SPLB0, DMA0 or C_MPLB_PRIO_
DMA1 for the MPLB interface (initial value of _SPLB0
0-4
See Notes ⁽⁴⁾ and ⁽⁶⁾.
1
DCR "ARB_XBC", field "PLBS0")
0 = Least Recently
MPLB interface arbitration mode (initial
C_MPLB_ARB_
Used (LRU)
value of DCR "ARB_XBC", field "MODE")
See Note ⁽¹⁰⁾.
MODE
1 = round-robin
0
2= fixed priority
Allow MBusy to block MPLB when
Tattribute[7] ("Sync") is asserted (initial value
C_MPLB_SYNC_
0 = disable Sync
0
of DCR "ARB_XBC", field "SYNCTATTR") ^TATTRIBUTE
1 = enable Sync
Maximum number of quad-words per burst
through crossbar to MPLB interface (used to
derive the initial value of DCR
C_MPLB_MAX_
1, 2, 4, 8, 16
8
"CFG_PLBS0" and "CFG_PLBS1", fields ^BURST
"THRPLBM" and "THWPLBM")
Allow locked transfers on MPLB (initial value ^{C_MPLB_ALLOW_}
of DCR "CFG_PLBM", field "LOCKXFER") _{LOCK_XFER}
0 = disallow,
1 = allow
1
Allow read address pipelining on MPLB
(initial value of DCR "CFG_PLBM", field
C_MPLB_READ_
0 = disallow,
1
"RPIPE") See Note ⁽¹⁰⁾.
PIPE_ENABLE
1 = allow
Allow write address pipelining on MPLB
(initial value of DCR "CFG_PLBM", field
"WPIPE")
C_MPLB_WRITE_
PIPE_ENABLE
0 = disallow,
1 = allow
1
Allow posted writes on MPLB and SPLB
interfaces (initial value of DCRs
"CFG_PLBM", "CFG_PLBS0" and
C_MPLB_WRITE_
POST_ENABLE
0 = disallow,
1 = allow
1
"CFG_PLBS1"; field "WPOST")
Point-to-Point interconnect mode on MPLB
(ignored by wrapper)
C_MPLB_P2P
0
[Note 2, 7]
0
SPLB0 Interface
SPLB0 Address bus width (ignored by
wrapper)
C_SPLB0_AWIDTH
32
See Note ⁽²⁾.
32
VHDL
Type
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
DS621 July 5, 2011
www.xilinx.com
6
Product Specification