DS571 Datasheet, PDF (9/16 Pages) Xilinx, Inc – LogiCORE IP XPS UART Lite

LogiCORE IP XPS UART Lite (v1.02.a)
Table 7: UART Lite Control Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
0 - 26
Reserved
N/A
0
27
Enable Intr
Write
’0’
28 - 29
30
Reserved
N/A
0
Rst Rx FIFO
Write
’0’
31
Rst Tx FIFO
Write
’0’
Description
Reserved
Enable Interrupt for the UART Lite
’0’ = Disable interrupt signal
’1’ = Enable interrupt signal
Reserved
Reset/Clear the Receive FIFO
Writing a ’1’ to this bit position clears the Receive
FIFO
’0’ = Do nothing
’1’ = Clear the Receive FIFO
Reset/Clear the Transmit FIFO
Writing a ’1’ to this bit position clears the Transmit
FIFO
’0’ = Do nothing
’1’ = Clear the Transmit FIFO
UART Lite Status Register (STAT_REG)
The UART Lite Status Register contains the status of the Receive and Transmit Data FIFO, if interrupts are enabled,
and if there are any errors. This is read only register. If a write request is issued to status register it will do nothing
but generate write acknowledgement. Bit assignment in the STAT_REG is shown in Figure 5 and described in
Table 8.
X-Ref Target - Figure 5
Reserved
Intr Enabled Rx FIFO
Valid Data
Frame Error
Tx FIFO
Empty
0
23 24 25 26 27 28 29 30 31
Overrun Rx FIFO Full
Error
Parity Error Tx FIFO Full
Figure 5: UART Lite Status Register
DS571 June 22, 2011
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Product Specification