DS571 Datasheet, PDF (14/16 Pages) Xilinx, Inc – LogiCORE IP XPS UART Lite

LogiCORE IP XPS UART Lite (v1.02.a)
X-Ref Target - Figure 8
MPMC XPS CDMA XPS CDMA DUT
MicroBlaze
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
MDM
Figure 8: Spartan-3A System
sp3_dsp_sys
The target FPGA was then filled with logic to drive the LUT and block RAM utilization to approximately 70% and
the I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target Fmax numbers are shown in Table 12.
Table 12: XPS UART Lite System Performance
Target FPGA
S3A700 -4
Target f_MAX (MHz)
90
V4FX60 -10
100
V5LXT50 -1
120
The target Fmax is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISE
Embedded Edition software (EDK).
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.
For information on pricing and availability of other Xilinx LogiCORE IP modules and software, contact your local
Xilinx sales representative.
Reference Documents
IBM CoreConnect 128-Bit Processor Local Bus, Architectural Specification (v4.6).
DS571 June 22, 2011
www.xilinx.com
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Product Specification