DS571 Datasheet, PDF (2/16 Pages) Xilinx, Inc – LogiCORE IP XPS UART Lite

LogiCORE IP XPS UART Lite (v1.02.a)
Functional Description
The XPS UART Lite performs parallel-to-serial conversion on characters received through PLB and
serial-to-parallel conversion on characters received from a serial peripheral.
The XPS UART Lite is capable of transmitting and receiving 8, 7, 6 or 5-bit characters, with 1-stop bit and odd, even
or no parity. The XPS UART Lite can transmit and receive independently.
The device can be configured and its status can be monitored via the internal register set. The XPS UART Lite
generates an interrupt when Receive FIFO becomes non-empty or when transmit FIFO becomes empty. This
interrupt can be masked by using an interrupt enable/disable signal.
The device contains a 16-bit programmable baud rate generator and independent 16-word Transmit and Receive
FIFOs. The FIFOs can be enabled or disabled through software control.
The XPS UART Lite modules are shown in the top-level block diagram in Figure 1.
X-Ref Target - Figure 1
PLB
PLB
Interface
PLB
Interface
Module
UART Lite
Register Module
Receive Data
FIFO
Transmit Data
FIFO
Status Register
(STAT_REG)
UART Control Module
RX
Module
BRG
TX
Module
Control Register
(CTRL_REG)
Control
Unit
RX
Serial
Interface
TX
Interrupt
Figure 1: Block Diagram of XPS UART Lite
The XPS UART Lite modules are described in the next sections:
PLB Interface Module: The PLB Interface Module provides the interface to the PLB and implements PLB protocol
logic. PLB Interface Module is a bidirectional interface between a user IP core and the PLB bus standard. To simplify
the process of attaching an XPS UART Lite to the PLB, the core makes use of a portable, pre-designed bus interface
called PLB Interface Module that takes care of the bus interface signals, bus protocols, and other interfaces.
UART Lite Register Module: The Register Module includes all memory-mapped registers (as shown in Figure 1).
It interfaces to the PLB through the PLB Interface Module. It consists of an 8-bit status register, an 8-bit control
register and a pair of 8-bit Transmit/Receive FIFOs. All registers are accessed directly from the PLB using the PLB
Interface Module.
UART Control Module: The UART Control Module consists of an RX module, a TX module, a parameterized baud
rate generator (BRG), and a Control Unit. It incorporates the state machine for initialization and start and stop bit
control logic.
DS571 June 22, 2011
www.xilinx.com
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Product Specification