DS571 Datasheet, PDF (5/16 Pages) Xilinx, Inc – LogiCORE IP XPS UART Lite

LogiCORE IP XPS UART Lite (v1.02.a)
XPS UART Lite Design Parameters
To allow the user to obtain an XPS UART Lite that is uniquely tailored for the system, certain features can be
parameterized in the XPS UART Lite design. This allows the user to configure a design that utilizes the resources
required by the system only and that operates with the best possible performance. The features that can be
parameterized in the XPS UART Lite design are as shown in Table 2.
Table 2: XPS UART Lite Design Parameters
Generic
Feature/Description
Parameter Name
Allowable Values
Default
Value
System Parameter
G1
Target FPGA family
C_FAMILY
spartan3e, aspartan3e,
spartan3,
aspartan3,
spartan3a, spartan3an,
aspartan3a,
spartan3adsp,
aspartan3adsp, virtex4,
qvirtex4, qrvirtex4, virtex5
virtex5
G2
System clock frequency (in C_SPLB_CLK_
integer (ex. 100000000) 100_
Hz) driving the UART Lite FREQ_HZ
000_
peripheral
000
PLB Parameters
G3
PLB Base Address
C_BASEADDR
Valid Address⁽¹⁾
None⁽³⁾
G4
PLB High Address
C_HIGHADDR
Valid Address⁽²⁾
None⁽³⁾
G5
PLB least significant address C_SPLB_AWIDTH
32
32
bus width
G6
PLB data width
C_SPLB_DWIDTH
32, 64, 128
32
G7
Selects point-to-point or
C_SPLB_P2P
shared bus topology
0 = Shared Bus Topology 0
1 = Point-to-Point Bus
Topology⁽⁴⁾
G8
PLB Master ID Bus Width C_SPLB_MID_
WIDTH
log₂(C_SPLB_NUM_
1
MASTERS) with a
minimum value of 1
G9
Number of PLB Masters
C_SPLB_NUM_
1 - 16
1
MASTERS
G10
Support Bursts
C_SPLB_SUPPORT_ 0
0
BURSTS
G11
Width of the Slave Data Bus C_SPLB_NATIVE_
32
32
DWIDTH
UART Lite Parameters
G12
Baud rate of the UART Lite in C_BAUDRATE
bits per second
integer (ex. 128000)
128_
000^<RD
Red>[5]
VHDL Type
string
Integer
std_logic_
vector
std_logic_
vector
integer
integer
integer
integer
integer
integer
integer
Integer
G13
The number of data bits in C_DATA_BITS
the serial frame
5-8
8
Integer
DS571 June 22, 2011
www.xilinx.com
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Product Specification