DS571 Datasheet, PDF (3/16 Pages) Xilinx, Inc – LogiCORE IP XPS UART Lite

LogiCORE IP XPS UART Lite (v1.02.a)
Interrupts
If interrupts are enabled, an interrupt is generated when one of these two conditions is true:
1. When the Receive FIFO goes from empty to not empty, such as when the first valid character is received in the
Receive FIFO
2. When the Transmit FIFO goes from not empty to empty, such as when the last character in the Transmit FIFO is
transmitted
XPS UART Lite I/O Signals
The XPS UART Lite I/O signals are listed and described in Table 1.
Table 1: XPS UART Lite I/O Signal Description
Port
Signal Name
Interface
I/O
Initial
State
System Signals
P1
SPLB_Clk
System
I
-
P2
SPLB_Rst
System
I
-
PLB Interface Signals
P3
PLB_ABus[0 : 31]
PLB
I
-
P4
PLB_PAValid
PLB
I
-
P5
PLB_masterID[0 :
PLB
I
-
C_SPLB_MID_WIDTH - 1]
P6
PLB_RNW
PLB
I
-
P7
PLB_BE[0 : (C_SPLB_DWIDTH/8) - PLB
I
-
1]
P8
PLB_size[0 : 3]
PLB
I
-
P9
PLB_type[0 : 2]
PLB
I
-
P10
PLB_wrDBus[0 :
C_SPLB_DWIDTH - 1]
P11
PLB_UABus[0 : 31]
P12
PLB_SAValid
P13
PLB_rdPrim
PLB
I
-
Unused PLB Interface Signals
PLB
I
-
PLB
I
-
PLB
I
-
P14
PLB_wrPrim
PLB
I
-
P15
PLB_abort
P16
PLB_busLock
P17
PLB_MSize[0 : 1]
P18
PLB_lockErr
P19
PLB_wrBurst
P20
PLB_rdBurst
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
Description
PLB clock
PLB reset, active high
PLB address bus
PLB primary address valid
PLB current master identifier
PLB read not write
PLB byte enables
PLB size of requested transfer
PLB transfer type
PLB write data bus
PLB upper address bits
PLB secondary address valid
PLB secondary to primary read
request indicator
PLB secondary to primary write
request indicator
PLB abort bus request
PLB bus lock
PLB data bus width indicator
PLB lock error
PLB burst write transfer
PLB burst read transfer
DS571 June 22, 2011
www.xilinx.com
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Product Specification