DS571 Datasheet, PDF (1/16 Pages) Xilinx, Inc – LogiCORE IP XPS UART Lite

DS571 June 22, 2011
LogiCORE IP XPS UART Lite
(v1.02.a)
Product Specification
Introduction
The Xilinx® XPS Universal Asynchronous Receiver
Transmitter (UART) Lite Interface connects to the PLB
(Processor Local Bus) and provides the controller
interface for asynchronous serial data transfer. This soft
IP core is designed to interface with the PLBV46.
Features
• PLB interface is based on PLB v4.6 specification
• Supports 8-bit bus interfaces
• One transmit and one receive channel (full duplex)
• 16-character Transmit FIFO and 16-character
Receive FIFO
• Configurable number of data bits in a character
(5-8)
• Configurable parity bit (odd or even)
• Configurable baud rate
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family⁽¹⁾
Virtex-5,
Virtex-4,
Spartan-3E, Automotive Spartan-3E, Spartan-3,
Automotive Spartan-3, Spartan-3A,
Spartan-3AN, Automotive Spartan-3A,
Spartan-3A DSP, Automotive Spartan-3A DSP
Supported User
Interfaces
PLB v46
Resources
Slices LUTs FFS Block RAMs
See Table 9, Table 10 and Table 11
Provided with Core
Documentation
Product Specification
Design Files
VHDL
Example Design
Not Provided
Test Bench
Not Provided
Constraints File
N/A
Simulation
Model
N/A
Tested Design Tools
Design Entry
Tools
ISE 13.2 software
Simulation
Mentor Graphics ModelSim ⁽²⁾
Synthesis Tools
XST 13.2
Support
Provided by Xilinx @ www.xilinx.com/support
1. For a complete listing of supported devices, see
IDS Embedded Edition Derivative Device Support for this core.
2. For the supported versions of the tool, see the ISE Design Suite
13: Release Notes Guide.
© Copyright 2009-2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of
Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
DS571 June 22, 2011
www.xilinx.com
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Product Specification