DS571 Datasheet, PDF (6/16 Pages) Xilinx, Inc – LogiCORE IP XPS UART Lite

LogiCORE IP XPS UART Lite (v1.02.a)
Table 2: XPS UART Lite Design Parameters (Cont’d)
Generic
Feature/Description
Parameter Name
Allowable Values
Default
Value
VHDL Type
G14
Determines whether parity is C_USE_PARITY
used or not
0 = Do not use parity
1
1 = Use parity
Integer
G15
If parity is used, determines C_ODD_PARITY
0 = Even parity
whether parity is odd or even
1 = Odd parity
1
Integer
Notes:
1. The user must set the values. The C_BASEADDR must be a multiple of the range, where the range is C_HIGHADDR -
C_BASEADDR + 1.
2. C_HIGHADDR - C_BASEADDR must be a power of 2 greater than equal to C_BASEADDR + 0xF.
3. No default value is specified to ensure that the actual value is set; that is, if the value is not set, a compiler error is generated.
4. Value of ’1’ is not supported in this core.
5. With a baud rate of 115200, the sample clock is 16 * 115200 = 1.8432 MHz. With the System clock C_CLK_FREQ running at 10
MHz, the integer ratio for driving the sample clock is 5 (rounding of [10/1.8432]). The UART Lite then divides the System clock by
5 resulting in 2 MHz for the sample clock. The baud rate error is (1.8432 - 2) /1.8432 => -8.5% which is outside the tolerance for
most UARTs. The issue is that the higher the baud rate and the lower the C_CLK_FREQ, the greater the error in the generated
baud rate of the UART Lite. Specifications for the baud rate error state that within 5% of the requested rate is considered
acceptable.
Allowable Parameter Combinations
The address range specified by C_BASEADDR and C_HIGHADDR must be a power of 2, and must be at least 0xF.
For example, if C_BASEADDR = 0xE0000000, C_HIGHADDR must be at least = 0xE000000F.
XPS UART Lite Parameter - Port Dependencies
The dependencies between the XPS UART Lite core design parameters and I/O signals are described in Table 3. In
addition, when certain features are parameterized out of the design, the related logic will no longer be a part of the
design. The unused input signals and related output signals are set to a specified value.
Table 3: XPS UART Lite Parameter-Port Dependencies
Generic
or Port
Name
Affects
Depends
Relationship Description
G6
C_SPLB_DWIDTH
G8
C_SPLB_MID_WIDTH
Design Parameters
P7, P10, P33 -
P5
G9
G9
C_SPLB_NUM_MASTERS
P36, P37, P38, -
P42
I/O Signals
P5
PLB_masterID[0 :
-
G8
C_SPLB_MID_WIDTH - 1]
P7
PLB_BE[0 : (C_SPLB_DWIDTH/8) -1] -
G6
P10
PLB_wrDBus[0 : C_SPLB_DWIDTH - 1] -
G6
P33
Sl_rdDBus[0 : C_SPLB_DWIDTH - 1] -
G6
Affects the number of bits in data bus
This value is calculated as:
log₂(C_SPLB_NUM_MASTERS) with
a minimum value of 1
Affects the number of PLB masters
Width of the PLB_mastedID varies
according to C_SPLB_MID_WIDTH
Width of the PLB_BE varies according
to C_SPLB_DWIDTH
Width of the PLB_wrDBus varies
according to C_SPLB_DWIDTH
Width of the Sl_rdDBus varies
according to C_SPLB_DWIDTH
DS571 June 22, 2011
www.xilinx.com
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Product Specification