DS571 Datasheet, PDF (11/16 Pages) Xilinx, Inc – LogiCORE IP XPS UART Lite

LogiCORE IP XPS UART Lite (v1.02.a)
Design Implementation
Target Technology
The intended target technology is Virtex®-4, Virtex-5 and Spartan®-3 family FPGAs.
Device Utilization and Performance Benchmarks
Core Performance
Because the XPS UART Lite core will be used with other design modules in the FPGA, the utilization and timing
numbers reported in this section are estimates only. When the XPS UART Lite core is combined with other designs
in the system, the utilization of FPGA resources and timing of the XPS UART Lite design will vary from the results
reported here.
The XPS UART Lite resource utilization for various parameter combinations measured with Virtex-4 FPGAs as the
target device are detailed in Table 9.
Table 9: Performance and Resource Utilization Benchmarks on Virtex-4 (xc4vlx25-10-ff668)
Parameter Values (other parameters at default value)
Device Resources
Performance
Slices
Slice
Flip-
Flops
LUTs
F_MAX (MHz)
32
100_000_000 19_200
5
FALSE FALSE
98
83
123
145
32
100_000_000 19_200
6
FALSE FALSE 100
84
127
132
32
100_000_000 19_200
7
FALSE FALSE 100
85
129
168
32
100_000_000 19_200
8
FALSE FALSE 101
86
131
122
32
40_000_000 38_400
8
FALSE FALSE 100
85
130
125
32
100_000_000 19_200
6
TRUE FALSE 104
90
134
117
32
100_000_000 19_200
7
TRUE FALSE 105
91
136
149
DS571 June 22, 2011
www.xilinx.com
11
Product Specification