DS571 Datasheet, PDF (4/16 Pages) Xilinx, Inc – LogiCORE IP XPS UART Lite

LogiCORE IP XPS UART Lite (v1.02.a)
Table 1: XPS UART Lite I/O Signal Description (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
P21
PLB_wrPendReq
PLB
I
-
P22
PLB_rdPendReq
PLB
I
-
P23
PLB_wrPendPri[0 : 1]
PLB
I
-
P24
PLB_rdPendPri[0 : 1]
PLB
I
-
P25
PLB_reqPri[0 : 1]
PLB
I
-
P26
PLB_TAttribute[0 : 15]
PLB
I
-
PLB Slave Interface Signals
P27
Sl_addrAck
PLB
O
0
P28
Sl_SSize[0 : 1]
PLB
O
0
P29
Sl_wait
PLB
O
0
P30
Sl_rearbitrate
PLB
O
0
P31
Sl_wrDAck
PLB
O
0
P32
Sl_wrComp
PLB
O
0
P33
Sl_rdDBus[0 : C_SPLB_DWIDTH - PLB
1]
O
0
P34
Sl_rdDAck
PLB
O
0
P35
Sl_rdComp
PLB
O
0
P36
Sl_MBusy[0 :
PLB
C_SPLB_NUM_MASTERS - 1]
O
0
P37
Sl_MWrErr[0 :
PLB
C_SPLB_NUM_MASTERS - 1]
O
0
P38
Sl_MRdErr[0 :
PLB
C_SPLB_NUM_MASTERS - 1]
O
0
Unused PLB Slave Interface Signals
P39
Sl_wrBTerm
PLB
O
0
P40
Sl_rdWdAddr[0 : 3]
PLB
O
0
P41
Sl_rdBTerm
PLB
O
0
P42
Sl_MIRQ[0 :
PLB
C_SPLB_NUM_MASTERS - 1]
O
0
UART Lite Interface Signals
P43
RX
UART Lite I
-
P44
TX
UART Lite O
0
P45
Interrupt
UART Lite O
0
Description
PLB pending bus write request
PLB pending bus read request
PLB pending write request priority
PLB pending read request priority
PLB current request priority
PLB transfer attribute
Slave address acknowledge
Slave data bus size
Slave wait
Slave bus rearbitrate
Slave write data acknowledge
Slave write transfer complete
Slave read data bus
Slave read data acknowledge
Slave read transfer complete
Slave busy
Slave write error
Slave read error
Slave terminate write burst transfer
Slave read word address
Slave terminate read burst transfer
Master interrupt request
Receive Data
Transmit Data
UART Interrupt
DS571 June 22, 2011
www.xilinx.com
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Product Specification