DS571 Datasheet, PDF (8/16 Pages) Xilinx, Inc – LogiCORE IP XPS UART Lite

LogiCORE IP XPS UART Lite (v1.02.a)
Table 5: Receive Data FIFO Bit Definitions
Bit(s)
Name
Core
Access
0 - [31-C_DATA_BITS]
Reserved
N/A
[(31-C_DATA_BITS)+1] - 31 Rx Data
Read
Reset
Value
0
0
Description
Reserved
UART Receive data
Transmit Data FIFO
This 16 entry deep FIFO contains data to be output by XPS UART Lite. The FIFO bit definitions are shown in
Table 6. Data to be transmitted is written into this register. This is write only location. Issuing a read request to
Transmit Data FIFO generates the read acknowledgement with zero data. Figure 3 shows the location for data on
the PLB when C_DATA_BITS is set to 8.
X-Ref Target - Figure 3
Tx Data
0
23 24
31
Reserved
Figure 3: Transmit Data FIFO (C_DATA_BITS = 8)
.
Table 6: Transmit Data FIFO Bit Definitions
Bit(s)
Name
Core
Access
0 - [31-C_DATA_BITS]
Reserved
N/A
[(31-C_DATA_BITS)+1] - 31 Tx Data
Write
Reset
Value
0
0
Description
Reserved
UART transmit data
UART Lite Control Register (CTRL_REG)
The UART Lite Control Register contains the Enable Interrupt bit and Reset pin for Receive and Transmit Data
FIFO. This is write only register. Issuing a read request to Control Register generates the read acknowledgement
with zero data. Figure 4 shows the bit assignment of the CTRL_REG. Table 7 describes this bit assignment.
X-Ref Target - Figure 4
0
Reserved
Figure 4: UART Lite Control Register
Reserved
Enable Intr Rst Tx FIFO
26 27 28 29 30 31
Rst Rx FIFO
DS571 June 22, 2011
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Product Specification