DS495 Datasheet, PDF(8/12 Page) Xilinx, Inc

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DS495 Datasheet, PDF (8/12 Pages) Xilinx, Inc – PCI Arbiter

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PCI Arbiter (v1.00a)

The PCI Specification allows a PCI master to start a transaction when its grant is asserted and the bus

is idle, without regard to the state of its request signal. That is when both Frame_n and Irdy_n are

deasserted the park master agent may initiate a bus transaction without asserting request, Req_n. The

PCI Arbiter must recognize and allow this situation. In this case, this master would maintain its status

as the last active master. This scenario is shown in Figure 6 with master agent number three as the park

master.

Figure Top x-ref 6

pci_clk

pci_rst_n

pci_req_n(0)

pci_req_n(1)

pci_req_n(2)

pci_req_n(3)

pci_req_n(4)

pci_req_n(5)

pci_frame

pci_irdy_n

pci_gnt_n(0)

pci_gnt_n(1)

pci_gnt_n(2)

pci_gnt_n(3)

pci_gnt_n(4)

pci_gnt_n(5)

Figure 6: Park Master Controlling the Bus Without First Requesting Access

X495 06 101306

Figure 7 shows the PCI_Arbiter operation for multiple requests. In this case, the park master is number

zero and all six connected master agents request access simultaneously. The PCI_Arbiter sequentially

grants access to agents zero through five. As master agent five is the last active master, it completes this

example as the park master.

Figure Top x-ref 7