DS495 Datasheet, PDF (3/12 Pages) Xilinx, Inc – PCI Arbiter

PCI Arbiter (v1.00a)
PCI_Arbiter Design Parameters
The PCI_Arbiter may be configured for particular systems by appropriately selecting features through
parameter values. This allows the user to craft a design with the minimum necessary resources that
operates at the best possible performance. The parameter features available in the Xilinx PCI_Arbiter
are shown in Table 2.
Table 2: PCI_Arbiter Design Parameters
Generic
Feature
Description
Parameter Name
Allowable Values
Default VHDL
Value
Type
Top Level
G1
Device family
C_FAMILY
virtex4, virtex5,
spartan3
virtex4
string
PCI Interface
G2
Number of PCI
Masters
C_NUM_PCI_MSTRS 2 - 8
4
integer
Allowable Parameter Combinations and Considerations
The allowed values for C_NUM_PCI_MSTRS are 2 through 8. The numbering of PCI Masters,
Requests, and Grants range from 0 to C_NUM_PCI_MSTRS - 1. Therefore, the default of value of 4
provides 4 PCI master agents numbered 0 through 3. Any number of PCI master agents from 2 through
8 work in all of the FPGA family types listed in Table 2.
Parameter/Port Dependencies
The width of two PCI_Arbiter signals depend upon the selected value C_NUM_PCI_MSTRS as
illustrated in Table 3.
Table 3: Parameter/Port Dependencies
Generic
or Port
Name
Affects Depends
Relationship Description
Design Parameters
G2 C_NUM_PCI_MSTRS P3, P4
C_NUM_PCI_MSTRS determines the number of
PCI requests and grants.
I/O Signals
P3
PCI_Req_n
G2
The number of PCI requests depends on
C_NUM_PCI_MSTRS.
P4
PCI_Gnt_n
G2
The number of PCI grants depends on
C_NUM_PCI_MSTRS.
DS495 April 8, 2009
www.xilinx.com
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Product Specification