DS495 Datasheet, PDF (5/12 Pages) Xilinx, Inc – PCI Arbiter

PCI Arbiter (v1.00a)
Behavioral Waveforms
These waveforms detail the operation of the PCI_Arbiter and depict the sequence of events for various
scenarios as PCI master agents compete for access to the PCI bus. They provide a consistent description
for the development of documentation, design, simulation, verification, and tests.
The first case, illustrated in Figure 2, represents the most simple operation for the PCI_Arbiter. In this
case, the PCI bus starts from an idle situation with the PCI_Arbiter providing grant to the last active
PCI master, agent number four in this example, for bus parking. The last active master is defined as the
most recent PCI master agent that correctly responded to grant by appropriately asserting
PCI_Frame_n for a bus transaction. The PCI master agent connected to PCI_Req_n(3) then requests
access to the PCI bus. After two PCI_Clk cycles, the PCI_Arbiter grants access by asserting
PCI_Gnt_n(3). Master agent number three responds with a bus transaction, initiated by asserting of
Frame_n and Irdy_n and terminated by deasserting PCI_Frame_n and PCI_Irdy_n. Notice that
PCI_Req_n(3) deasserts in the same clock cycle that PCI_Frame_n asserts. This is the minimum
duration for a master to assert a request and be granted the bus. Master agent three becomes the last
active master and the PCI_Arbiter parks on this agent while the PCI bus goes idle. This is indicated by
the continued assertion of PCI_Gnt_n(3).
Figure Top x-ref 2
pci_clk
pci_rst_n
pci_req_n(0)
pci_req_n(1)
pci_req_n(2)
pci_req_n(3)
pci_req_n(4)
pci_req_n(5)
pci_frame
pci_irdy_n
pci_gnt_n(0)
pci_gnt_n(1)
pci_gnt_n(2)
pci_gnt_n(3)
pci_gnt_n(4)
pci_gnt_n(5)
Figure 2: Simple, Single Request and Grant
X495_02_101106
DS495 April 8, 2009
www.xilinx.com
5
Product Specification